From b170d374eef41113f8b5e9255ed2c9b3a3a2f300 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 29 Nov 2023 16:46:25 +0800 Subject: [PATCH] =?UTF-8?q?fix(csr):=20ret=E4=BF=A1=E5=8F=B7=E9=94=99?= =?UTF-8?q?=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/Csr.scala | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index 9320094..9182431 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -209,6 +209,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val mem_inst = mem_inst_info.inst val mem_valid = mem_inst_info.valid val mem_addr = mem_inst(31, 20) + // 不带前缀的信号为exe阶段的信号 val valid = io.executeUnit.in.valid val op = io.executeUnit.in.inst_info.op val fusel = io.executeUnit.in.inst_info.fusel @@ -248,10 +249,13 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata) // CSR inst decode - val ret = Wire(Bool()) - val isMret = mem_addr === privMret && op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid - val isSret = mem_addr === privSret && op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid - val isUret = mem_addr === privUret && op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid + val ret = Wire(Bool()) + val isMret = + mem_addr === privMret && mem_inst_info.op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid + val isSret = + mem_addr === privSret && mem_inst_info.op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid + val isUret = + mem_addr === privUret && mem_inst_info.op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid ret := isMret || isSret || isUret val has_exception = mem_ex.exception.asUInt.orR