style(tlb): 加上p的前缀表示物理地址

chisel/playground/src/cache/DCache.scala

@@ -198,7 +198,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
     tagRam.io.waddr := victim.index
     tagRam.io.wdata := tag_wdata
 
-    tag_compare_valid(i) := tag(i) === io.cpu.tlb.tag && valid(index)(i) && io.cpu.tlb.translation_ok
+    tag_compare_valid(i) := tag(i) === io.cpu.tlb.ptag && valid(index)(i) && io.cpu.tlb.translation_ok
     cache_data_forward(i) := Mux(
       last_waddr === bank_addr,
       ((last_wstrb(i) & last_wdata) | (data(i) & (~last_wstrb(i)))),
@@ -290,8 +290,8 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
               writeFifo.io.enq.valid := true.B
               writeFifo.io.enq.bits.addr := Mux(
                 io.cpu.rlen === 2.U,
-                Cat(io.cpu.tlb.pa(31, 2), 0.U(2.W)),
+                Cat(io.cpu.tlb.paddr(31, 2), 0.U(2.W)),
-                io.cpu.tlb.pa
+                io.cpu.tlb.paddr
               )
               writeFifo.io.enq.bits.size := io.cpu.rlen
               writeFifo.io.enq.bits.strb := io.cpu.wstrb
@@ -303,7 +303,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
               current_mmio_write_saved := false.B
             }
           }.elsewhen(!(writeFifo.io.deq.valid || writeFifo_axi_busy)) {
-            ar.addr := Mux(io.cpu.rlen === 2.U, Cat(io.cpu.tlb.pa(31, 2), 0.U(2.W)), io.cpu.tlb.pa)
+            ar.addr := Mux(io.cpu.rlen === 2.U, Cat(io.cpu.tlb.paddr(31, 2), 0.U(2.W)), io.cpu.tlb.paddr)
             ar.len  := 0.U
             ar.size := io.cpu.rlen
             arvalid := true.B
@@ -460,7 +460,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
             }
           }
           when(!ar_handshake) {
-            ar.addr                   := Cat(io.cpu.tlb.pa(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
+            ar.addr                   := Cat(io.cpu.tlb.paddr(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
             ar.len                    := cached_len.U
             ar.size                   := cached_size.U // 8 字节
             arvalid                   := true.B
@@ -468,7 +468,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
             ar_handshake              := true.B
             victim.wstrb(replace_way) := ~0.U(AXI_STRB_WID.W)
             tag_wstrb(replace_way)    := true.B
-            tag_wdata                 := io.cpu.tlb.tag
+            tag_wdata                 := io.cpu.tlb.ptag
           }
           when(io.axi.ar.fire) {
             tag_wstrb(replace_way) := false.B

chisel/playground/src/cache/ICache.scala

@@ -121,7 +121,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   )
 
   // * cache hit * //
-  val tag_compare_valid   = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.tag && valid(i)(virtual_index)))
+  val tag_compare_valid   = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.ptag && valid(i)(virtual_index)))
   val cache_hit           = tag_compare_valid.contains(true.B)
   val cache_hit_available = cache_hit && io.cpu.tlb.translation_ok && !io.cpu.tlb.uncached
   val select_way          = tag_compare_valid(1) // 1路命中时值为1，0路命中时值为0 //TODO:支持更多路数
@@ -236,14 +236,14 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
           tlb_fill := true.B
         }.elsewhen(io.cpu.tlb.uncached) {
           state   := s_uncached
-          ar.addr := io.cpu.tlb.pa
+          ar.addr := io.cpu.tlb.paddr
           ar.len  := uncached_len.U
           ar.size := uncached_size.U
           arvalid := true.B
         }.elsewhen(!cache_hit) {
           state := s_replace
           // 取指时按bank块取指
-          ar.addr := Cat(io.cpu.tlb.pa(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
+          ar.addr := Cat(io.cpu.tlb.paddr(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
           ar.len  := cached_len.U
           ar.size := cached_size.U
           arvalid := true.B
@@ -252,7 +252,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
           replace_wstrb(replace_way).map(_.map(_ := false.B))
           replace_wstrb(replace_way)(0)(0)  := true.B // 从第一个bank的第一个指令块开始写入
           tag_wstrb(replace_way)            := true.B
-          tag_wdata                         := io.cpu.tlb.tag
+          tag_wdata                         := io.cpu.tlb.ptag
           valid(replace_way)(virtual_index) := true.B
         }.elsewhen(!io.cpu.icache_stall) {
           replace_way := ~select_way

chisel/playground/src/cache/mmu/DTlbL1.scala

@@ -18,8 +18,8 @@ class DTlbL1 extends Module {
   io.cache.translation_ok := true.B
   io.cache.hit            := true.B
   io.cache.tlb1_ok        := true.B
-  io.cache.tag            := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
+  io.cache.ptag           := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
-  io.cache.pa             := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
+  io.cache.paddr          := Cat(io.cache.ptag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
 
   println("----------------------------------------")
   println("DTlbL1")

chisel/playground/src/cache/mmu/ITlbL1.scala

@@ -17,8 +17,8 @@ class ITlbL1 extends Module {
   io.cache.uncached       := AddressSpace.isMMIO(io.addr)
   io.cache.translation_ok := true.B
   io.cache.hit            := true.B
-  io.cache.tag            := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
+  io.cache.ptag            := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
-  io.cache.pa             := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
+  io.cache.paddr             := Cat(io.cache.ptag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
 
   println("----------------------------------------")
   println("ITlbL1")

chisel/playground/src/defines/TlbBundles.scala

@@ -122,8 +122,8 @@ class Tlb_ICache extends Bundle {
 
   val translation_ok = Output(Bool())
   val hit            = Output(Bool())
-  val tag            = Output(UInt(cacheConfig.tagWidth.W))
+  val ptag            = Output(UInt(cacheConfig.tagWidth.W))
-  val pa             = Output(UInt(PADDR_WID.W))
+  val paddr             = Output(UInt(PADDR_WID.W))
 }
 
 class Tlb_DCache extends Bundle {
@@ -135,6 +135,6 @@ class Tlb_DCache extends Bundle {
 
   val translation_ok = Output(Bool())
   val hit            = Output(Bool())
-  val tag            = Output(UInt(cacheConfig.tagWidth.W))
+  val ptag            = Output(UInt(cacheConfig.tagWidth.W))
-  val pa             = Output(UInt(PADDR_WID.W))
+  val paddr             = Output(UInt(PADDR_WID.W))
 }