From aaf97820d49044ef38c4cb103a751ada080ca032 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 11 Mar 2024 19:27:23 +0800 Subject: [PATCH] =?UTF-8?q?fix(csr):=20=E4=BF=AE=E5=A4=8Dmem=E7=BA=A7valid?= =?UTF-8?q?=E6=97=A0=E6=95=88=E6=97=B6=E4=BB=8D=E4=BD=BF=E7=94=A8ex?= =?UTF-8?q?=E4=BF=A1=E6=81=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/fu/Csr.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala index cc0899c..9f09f78 100644 --- a/chisel/playground/src/pipeline/execute/fu/Csr.scala +++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala @@ -265,8 +265,8 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst { val mem_valid = mem_inst_info.valid val mem_addr = mem_inst(31, 20) - val raise_exception = mem_ex.exception.asUInt.orR - val raise_interrupt = mem_ex.interrupt.asUInt.orR + val raise_exception = mem_ex.exception.asUInt.orR && mem_valid + val raise_interrupt = mem_ex.interrupt.asUInt.orR && mem_valid val raise_exc_int = raise_exception || raise_interrupt // 不带前缀的信号为exe阶段的信号 val valid = io.executeUnit.in.valid && !io.memoryUnit.out.flush // mem发生flush时，清刷掉exe的信号