From a8fe6f7a9c4ee6a0e10d623a3f3a897aa5e64bf6 Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 23 Nov 2023 13:40:17 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E5=BC=82=E5=B8=B8=E7=9B=B8?= =?UTF-8?q?=E5=85=B3=E4=BF=A1=E5=8F=B7=E5=90=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/defines/Bundles.scala | 2 +- chisel/playground/src/defines/Const.scala | 2 +- .../src/pipeline/decoder/DecoderUnit.scala | 36 +++++++++---------- .../playground/src/pipeline/execute/Csr.scala | 4 +-- .../pipeline/execute/ExeAccessMemCtrl.scala | 8 ++--- .../src/pipeline/execute/ExecuteUnit.scala | 2 +- .../playground/src/pipeline/execute/Fu.scala | 2 +- .../pipeline/memory/DataMemoryAccess.scala | 6 ++-- .../src/pipeline/memory/MemoryUnit.scala | 4 +-- .../pipeline/writeback/WriteBackUnit.scala | 6 ++-- 10 files changed, 36 insertions(+), 36 deletions(-) diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 3f18046..f9f7e4c 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -7,7 +7,7 @@ import cpu.defines.Const._ import cpu.CpuConfig class ExceptionInfo extends Bundle { - val excode = Vec(EXCODE_WID, Bool()) + val exception = Vec(EXC_WID, Bool()) val interrupt = Vec(INT_WID, Bool()) val tval = UInt(XLEN.W) } diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index 52a1f42..ee5db6d 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -19,7 +19,7 @@ trait Constants extends CoreParameter { val EXT_INT_WID = 3 val INT_WID = 12 - val EXCODE_WID = 16 + val EXC_WID = 16 // div val DIV_CTRL_WID = 2 diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index 743b66c..c4f6d23 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -127,21 +127,21 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti forwardCtrl.out.inst(0).src2.rdata, decoder(0).io.out.inst_info.imm ) - io.executeStage.inst0.ex.excode.map(_ := false.B) - io.executeStage.inst0.ex.excode(illegalInstr) := !inst_info(0).inst_valid - io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err - io.executeStage.inst0.ex.excode(instrAddrMisaligned) := io.instFifo.inst(0).addr_err - io.executeStage.inst0.ex.excode(breakPoint) := inst_info(0).inst(31, 20) === privEbreak && + io.executeStage.inst0.ex.exception.map(_ := false.B) + io.executeStage.inst0.ex.exception(illegalInstr) := !inst_info(0).inst_valid + io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err + io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err + io.executeStage.inst0.ex.exception(breakPoint) := inst_info(0).inst(31, 20) === privEbreak && inst_info(0).op === CSROpType.jmp - io.executeStage.inst0.ex.excode(ecallM) := inst_info(0).inst(31, 20) === privEcall && + io.executeStage.inst0.ex.exception(ecallM) := inst_info(0).inst(31, 20) === privEcall && inst_info(0).op === CSROpType.jmp && priv_mode === ModeM - io.executeStage.inst0.ex.excode(ecallS) := inst_info(0).inst(31, 20) === privEcall && + io.executeStage.inst0.ex.exception(ecallS) := inst_info(0).inst(31, 20) === privEcall && inst_info(0).op === CSROpType.jmp && priv_mode === ModeS - io.executeStage.inst0.ex.excode(ecallU) := inst_info(0).inst(31, 20) === privEcall && + io.executeStage.inst0.ex.exception(ecallU) := inst_info(0).inst(31, 20) === privEcall && inst_info(0).op === CSROpType.jmp && priv_mode === ModeU io.executeStage.inst0.ex.tval := Mux( - io.executeStage.inst0.ex.excode(instrAccessFault) || io.executeStage.inst0.ex.excode(instrAddrMisaligned), + io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned), io.instFifo.inst(0).pc, 0.U ) @@ -165,21 +165,21 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti forwardCtrl.out.inst(1).src2.rdata, decoder(1).io.out.inst_info.imm ) - io.executeStage.inst1.ex.excode.map(_ := false.B) - io.executeStage.inst1.ex.excode(illegalInstr) := !inst_info(1).inst_valid - io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err - io.executeStage.inst1.ex.excode(instrAddrMisaligned) := io.instFifo.inst(1).addr_err - io.executeStage.inst1.ex.excode(breakPoint) := inst_info(1).inst(31, 20) === privEbreak && + io.executeStage.inst1.ex.exception.map(_ := false.B) + io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_valid + io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err + io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err + io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak && inst_info(1).op === CSROpType.jmp - io.executeStage.inst1.ex.excode(ecallM) := inst_info(1).inst(31, 20) === privEcall && + io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall && inst_info(1).op === CSROpType.jmp && priv_mode === ModeM - io.executeStage.inst1.ex.excode(ecallS) := inst_info(1).inst(31, 20) === privEcall && + io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall && inst_info(1).op === CSROpType.jmp && priv_mode === ModeS - io.executeStage.inst1.ex.excode(ecallU) := inst_info(1).inst(31, 20) === privEcall && + io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall && inst_info(1).op === CSROpType.jmp && priv_mode === ModeU io.executeStage.inst1.ex.tval := Mux( - io.executeStage.inst1.ex.excode(instrAccessFault) || io.executeStage.inst1.ex.excode(instrAddrMisaligned), + io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned), io.instFifo.inst(1).pc, 0.U ) diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index 2b35438..d24f98a 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -183,8 +183,8 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val priv_mode = RegInit(Priv.m) // 当前特权模式 // 优先使用inst0的信息 - val exc_sel = io.memoryUnit.in.inst(0).ex.excode.asUInt.orR || - !io.memoryUnit.in.inst(1).ex.excode.asUInt.orR + val exc_sel = io.memoryUnit.in.inst(0).ex.exception.asUInt.orR || + !io.memoryUnit.in.inst(1).ex.exception.asUInt.orR val pc = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc) val exc = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex) val valid = io.executeUnit.in.valid(0) diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala index 6f76524..ddfe2dd 100644 --- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala +++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala @@ -76,12 +76,12 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module { for (i <- 0 until config.fuNum) { val store_inst = LSUOpType.isStore(io.inst(i).inst_info.op) io.inst(i).ex.out := io.inst(i).ex.in - io.inst(i).ex.out.excode(loadAddrMisaligned) := store_inst && !addr_aligned(i) - io.inst(i).ex.out.excode(storeAddrMisaligned) := !store_inst && !addr_aligned(i) + io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i) + io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i) } io.inst(0).mem_sel := (LSUOpType.isStore(io.inst(0).inst_info.op) || LSUOpType.isLoad(io.inst(0).inst_info.op)) && - !io.inst(0).ex.out.excode.asUInt.orR + !io.inst(0).ex.out.exception.asUInt.orR io.inst(1).mem_sel := (LSUOpType.isStore(io.inst(1).inst_info.op) || LSUOpType.isLoad(io.inst(1).inst_info.op)) && - !io.inst(0).ex.out.excode.asUInt.orR && !io.inst(1).ex.out.excode.asUInt.orR + !io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR } diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 58961c1..921ef5c 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -45,7 +45,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) io.csr.in.inst_info(0) := Mux( - !io.executeStage.inst0.ex.excode.asUInt.orR, + !io.executeStage.inst0.ex.exception.asUInt.orR, io.executeStage.inst0.inst_info, 0.U.asTypeOf(new InstInfo()) ) diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index a71c75d..f71f7e6 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -57,7 +57,7 @@ class Fu(implicit val config: CpuConfig) extends Module { // alu(i).io.div.result := div.result alu(i).io.csr_rdata := io.csr_rdata(i) io.inst(i).ex.out := io.inst(i).ex.in - io.inst(i).ex.out.excode := io.inst(i).ex.in.excode + io.inst(i).ex.out.exception := io.inst(i).ex.in.exception } // mul.src1 := Mux(io.inst(0).mul_en, io.inst(0).src_info.src1_data, io.inst(1).src_info.src1_data) diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala index 6410c0a..0e770b0 100644 --- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala +++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala @@ -41,9 +41,9 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module { val mem_wdata = io.memoryUnit.in.mem_wdata val op = io.memoryUnit.in.inst_info.op io.dataMemory.out.en := io.memoryUnit.in.mem_en && - (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).excode.asUInt.orR || - io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).excode.asUInt.orR && - !io.memoryUnit.in.ex(1).excode.asUInt.orR) + (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).exception.asUInt.orR || + io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).exception.asUInt.orR && + !io.memoryUnit.in.ex(1).exception.asUInt.orR) io.dataMemory.out.addr := mem_addr val rdata = LookupTree( mem_addr(2, 0), diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index fd9cdcb..c5e963b 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -60,7 +60,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.memoryStage.inst0.rd_info.wdata ) io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex - io.writeBackStage.inst0.ex.excode := io.memoryStage.inst0.ex.excode + io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info @@ -70,7 +70,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.memoryStage.inst1.rd_info.wdata ) io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex - io.writeBackStage.inst1.ex.excode := io.memoryStage.inst1.ex.excode + io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala index 19495da..243fdfd 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala @@ -16,13 +16,13 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module { }) io.regfile(0).wen := io.writeBackStage.inst0.inst_info.reg_wen && - io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.excode.asUInt.orR + io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.exception.asUInt.orR io.regfile(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel) io.regfile(1).wen := io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go && - !io.writeBackStage.inst0.ex.excode.asUInt.orR && !io.writeBackStage.inst1.ex.excode.asUInt.orR + !io.writeBackStage.inst0.ex.exception.asUInt.orR && !io.writeBackStage.inst1.ex.exception.asUInt.orR io.regfile(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel) @@ -46,7 +46,7 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module { io.debug.wb_pc := Mux( clock.asBool, io.writeBackStage.inst0.pc, - Mux(io.writeBackStage.inst0.ex.excode.asUInt.orR, 0.U, io.writeBackStage.inst1.pc) + Mux(io.writeBackStage.inst0.ex.exception.asUInt.orR, 0.U, io.writeBackStage.inst1.pc) ) io.debug.wb_rf_wen := Mux( clock.asBool,