yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix(exe): 修复tval更新错误

This commit is contained in:
Liphen 2023-12-01 15:24:35 +08:00
parent ed6c3221e8
commit a08eb20f88
1 changed files with 10 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -113,9 +113,10 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.fetchUnit.target := MuxCase( io.fetchUnit.target := MuxCase(
io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧 io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
Seq( Seq(
(fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target, (fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
(fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U), (fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U),
(io.executeStage.inst0.jb_info.jump_regiser) -> ((io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data) & ~1.U(XLEN.W)), (io.executeStage.inst0.jb_info.jump_regiser) -> ((io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data) & ~1
.U(XLEN.W))
) )
) )
@ -152,13 +153,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
) )
io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) || io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) ||
io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR
io.memoryStage.inst0.ex.tval := MuxCase( when(io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR) {
io.executeStage.inst0.ex.tval, io.memoryStage.inst0.ex.tval := io.fetchUnit.target
Seq( }
(io.executeStage.inst0.ex.exception(instrAddrMisaligned)) -> io.executeStage.inst0.ex.tval,
(io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR) -> io.fetchUnit.target
)
)
io.memoryStage.inst1.pc := io.executeStage.inst1.pc io.memoryStage.inst1.pc := io.executeStage.inst1.pc
io.memoryStage.inst1.info := io.executeStage.inst1.info io.memoryStage.inst1.info := io.executeStage.inst1.info
@ -183,13 +180,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
) )
io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) || io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) ||
io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR
io.memoryStage.inst1.ex.tval := MuxCase( when(io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR) {
io.executeStage.inst1.ex.tval, io.memoryStage.inst1.ex.tval := io.fetchUnit.target
Seq( }
(io.executeStage.inst1.ex.exception(instrAddrMisaligned)) -> io.executeStage.inst1.ex.tval,
(io.fetchUnit.branch && io.fetchUnit.target(1, 0).orR) -> io.fetchUnit.target
)
)
io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr