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feat(csr): 修改misa的ext段

This commit is contained in:
Liphen 2023-12-18 16:59:25 +08:00
parent 534e608337
commit 90efc32bca
4 changed files with 16 additions and 7 deletions
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3
chisel/playground/src/CpuConfig.scala
View File

@ -7,9 +7,10 @@ case class CpuConfig(
// 指令集
val isRV32: Boolean = false, // 是否为RV32
val hasMExtension: Boolean = true, // 是否有乘除法单元
val hasAExtension: Boolean = true, // 是否有原子指令
// 特权模式
val hasSMode: Boolean = false, // 是否有S模式
val hasUMode: Boolean = false, // 是否有U模式
val hasUMode: Boolean = true, // 是否有U模式
// 模块配置
val hasCommitBuffer: Boolean = true, // 是否有提交缓存
val decoderNum: Int = 2, // 同时访问寄存器的指令数

8
chisel/playground/src/defines/Const.scala
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@ -76,10 +76,12 @@ object Const extends Constants with AXIConst with HasExceptionNO
object Instructions extends HasInstrType with CoreParameter {
def NOP = 0x00000013.U
val DecodeDefault = List(InstrN, FuType.csr, CSROpType.jmp)
def DecodeTable = RVIInstr.table ++ (if (config.hasMExtension) RVMInstr.table else Array.empty) ++
def DecodeTable = RVIInstr.table ++
(if (config.hasMExtension) RVMInstr.table else Array.empty) ++
(if (config.hasAExtension) RVAInstr.table else Array.empty) ++
Priviledged.table ++
RVAInstr.table ++
RVZicsrInstr.table ++ RVZifenceiInstr.table
RVZicsrInstr.table ++
RVZifenceiInstr.table
}
object AddressSpace extends CoreParameter {

4
chisel/playground/src/defines/isa/RVM.scala
View File

@ -30,7 +30,7 @@ object RV32MInstr extends HasInstrType with CoreParameter {
REM -> List(InstrR, FuType.mdu, MDUOpType.rem),
REMU -> List(InstrR, FuType.mdu, MDUOpType.remu)
)
val table = mulTable ++ (if (config.hasMExtension) divTable else Array.empty)
val table = mulTable ++ divTable
}
object RV64MInstr extends HasInstrType with CoreParameter {
@ -49,7 +49,7 @@ object RV64MInstr extends HasInstrType with CoreParameter {
REMW -> List(InstrR, FuType.mdu, MDUOpType.remw),
REMUW -> List(InstrR, FuType.mdu, MDUOpType.remuw)
)
val table = mulTable ++ (if (config.hasMExtension) divTable else Array.empty)
val table = mulTable ++ divTable
}
object RVMInstr extends CoreParameter {

8
chisel/playground/src/pipeline/execute/Csr.scala
View File

@ -69,7 +69,13 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val misa_init = Wire(new Misa())
misa_init := 0.U.asTypeOf(new Misa())
misa_init.mxl := 2.U
misa_init.extensions := "h101100".U
def getMisaExt(ext: Char): UInt = {1.U << (ext.toInt - 'a'.toInt)}
var extensions = List('i')
if(config.hasMExtension){ extensions = extensions :+ 'm'}
if(config.hasAExtension){ extensions = extensions :+ 'a'}
if(config.hasSMode){ extensions = extensions :+ 's'}
if(config.hasUMode){ extensions = extensions :+ 'u'}
misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i))
val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器
val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器
val mtvec = RegInit(0.U(XLEN.W)) // 中断向量基址寄存器