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增加mmio

This commit is contained in:
Liphen 2023-12-13 17:59:38 +08:00
parent 6bd22ee617
commit 908fd0a377
3 changed files with 18 additions and 57 deletions
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59
chisel/playground/src/defines/Const.scala
View File

@ -8,6 +8,7 @@ trait CoreParameter {
def config = new CpuConfig
val XLEN = if (config.isRV32) 32 else 64
val VADDR_WID = 32
val PADDR_WID = 32
}
trait Constants extends CoreParameter {
@ -44,47 +45,6 @@ trait Constants extends CoreParameter {
val AREG_NUM = 32
val REG_ADDR_WID = 5
val DATA_WID = XLEN
// CSR寄存器
// CSR Register (5.w), Select (3.w)
val CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0
val CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0
val CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0
val CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0
val CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0
// val CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1
// val CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2
val CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0
// val CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1
val CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0
// val CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0
val CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0
val CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7)
val CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0
val CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7)
val CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0
// val CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1
// val CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2
// val CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3
val CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0
val CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0
val CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0
val CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1
// val CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2
// val CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3
val CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0
val CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1
// val CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2
// val CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3
// val CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7)
// val CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0
val CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0
val CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0
val CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0
val CSR_ADDR_WID = 8
val PTEBASE_WID = 9
}
trait AXIConst {
@ -121,3 +81,20 @@ object Instructions extends HasInstrType with CoreParameter {
RVAInstr.table ++
RVZicsrInstr.table ++ RVZifenceiInstr.table
}
object AddressSpace extends CoreParameter {
// (start, size)
// address out of MMIO will be considered as DRAM
def mmio = List(
(0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC
(0x40000000L, 0x40000000L) // external devices
)
def isMMIO(addr: UInt) = mmio
.map(range => {
require(isPow2(range._2))
val bits = log2Up(range._2)
(addr ^ range._1.U)(PADDR_WID - 1, bits) === 0.U
})
.reduce(_ || _)
}

4
chisel/playground/src/defines/isa/Instructions.scala
View File

@ -79,10 +79,6 @@ object ALUOpType {
def bltu = "b0010110".U
def bgeu = "b0010111".U
// for RAS
def call = "b1011100".U
def ret = "b1011110".U
def isAdd(func: UInt) = func(6)
def isBru(func: UInt) = func(4)
def isBranch(func: UInt) = isBru(func) && !func(3)

12
chisel/playground/src/defines/isa/RVI.scala
View File

@ -78,18 +78,6 @@ object RV32I_BRUInstr extends HasInstrType {
BGEU -> List(InstrB, FuType.bru, ALUOpType.bgeu)
)
val bruFuncTobtbTypeTable = List(
ALUOpType.beq -> BTBtype.B,
ALUOpType.bne -> BTBtype.B,
ALUOpType.blt -> BTBtype.B,
ALUOpType.bge -> BTBtype.B,
ALUOpType.bltu -> BTBtype.B,
ALUOpType.bgeu -> BTBtype.B,
ALUOpType.call -> BTBtype.J,
ALUOpType.ret -> BTBtype.R,
ALUOpType.jal -> BTBtype.J,
ALUOpType.jalr -> BTBtype.I
)
}
object RV32I_LSUInstr extends HasInstrType {