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修改fu

This commit is contained in:
Liphen 2023-11-20 16:23:46 +08:00
parent 2865b6e64c
commit 90654aac2f
4 changed files with 62 additions and 98 deletions
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1
chisel/playground/src/defines/Bundles.scala
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@ -33,7 +33,6 @@ class InstInfo extends Bundle {
val reg_waddr = UInt(REG_ADDR_WID.W) val reg_waddr = UInt(REG_ADDR_WID.W)
val imm = UInt(XLEN.W) val imm = UInt(XLEN.W)
val dual_issue = Bool() val dual_issue = Bool()
val branch_link = Bool()
val inst = UInt(INST_WID.W) val inst = UInt(INST_WID.W)
} }

1
chisel/playground/src/pipeline/decoder/Decoder.scala
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@ -67,5 +67,4 @@ class Decoder extends Module with HasInstrType {
) )
io.out.inst_info.dual_issue := false.B io.out.inst_info.dual_issue := false.B
io.out.inst_info.inst := inst io.out.inst_info.inst := inst
io.out.inst_info.branch_link := VecInit(ALUOpType.jal, ALUOpType.jalr).contains(fuOpType)
} }

147
chisel/playground/src/pipeline/execute/Fu.scala
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@ -1,75 +1,62 @@
// package cpu.pipeline.execute package cpu.pipeline.execute
// import chisel3._ import chisel3._
// import chisel3.util._ import chisel3.util._
// import cpu.defines._ import cpu.defines._
// import cpu.defines.Const._ import cpu.defines.Const._
// import cpu.CpuConfig import cpu.CpuConfig
// class Fu(implicit val config: CpuConfig) extends Module { class Fu(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle { val io = IO(new Bundle {
// val ctrl = new ExecuteFuCtrl() val ctrl = new ExecuteFuCtrl()
// val inst = Vec( val inst = Vec(
// config.decoderNum, config.decoderNum,
// new Bundle { new Bundle {
// val pc = Input(UInt(PC_WID.W)) val pc = Input(UInt(PC_WID.W))
// val hilo_wen = Input(Bool()) val hilo_wen = Input(Bool())
// val mul_en = Input(Bool()) val mul_en = Input(Bool())
// val div_en = Input(Bool()) val div_en = Input(Bool())
// val inst_info = Input(new InstInfo()) val inst_info = Input(new InstInfo())
// val src_info = Input(new SrcInfo()) val src_info = Input(new SrcInfo())
// val ex = new Bundle { val ex = new Bundle {
// val in = Input(new ExceptionInfo()) val in = Input(new ExceptionInfo())
// val out = Output(new ExceptionInfo()) val out = Output(new ExceptionInfo())
// } }
// val result = Output(UInt(DATA_WID.W)) val result = Output(UInt(DATA_WID.W))
// }, }
// ) )
// val csr_rdata = Input(Vec(config.fuNum, UInt(DATA_WID.W))) val csr_rdata = Input(Vec(config.fuNum, UInt(DATA_WID.W)))
// val stall_req = Output(Bool()) val stall_req = Output(Bool())
// val branch = new Bundle { val branch = new Bundle {
// val pred_branch = Input(Bool()) val pred_branch = Input(Bool())
// val branch = Output(Bool()) val branch = Output(Bool())
// val pred_fail = Output(Bool()) val pred_fail = Output(Bool())
// } }
// val llbit = Output(Bool()) })
// val statistic = if (!config.build) Some(new BranchPredictorUnitStatistic()) else None val alu = Seq.fill(config.decoderNum)(Module(new Alu()))
// })
// val alu = Seq.fill(config.decoderNum)(Module(new Alu()))
// val mul = Module(new Mul()).io // val mul = Module(new Mul()).io
// val div = Module(new Div()).io // val div = Module(new Div()).io
// val hilo = Module(new HiLo()).io val branchCtrl = Module(new BranchCtrl()).io
// val branchCtrl = Module(new BranchCtrl()).io
// val llbit = Module(new LLbit()).io
// branchCtrl.in.inst_info := io.inst(0).inst_info branchCtrl.in.inst_info := io.inst(0).inst_info
// branchCtrl.in.src_info := io.inst(0).src_info branchCtrl.in.src_info := io.inst(0).src_info
// branchCtrl.in.pred_branch := io.branch.pred_branch branchCtrl.in.pred_branch := io.branch.pred_branch
// io.branch.branch := branchCtrl.out.branch io.branch.branch := branchCtrl.out.branch
// io.branch.pred_fail := branchCtrl.out.pred_fail io.branch.pred_fail := branchCtrl.out.pred_fail
// for (i <- 0 until (config.fuNum)) { for (i <- 0 until (config.fuNum)) {
// alu(i).io.inst_info := io.inst(i).inst_info alu(i).io.inst_info := io.inst(i).inst_info
// alu(i).io.src_info := io.inst(i).src_info alu(i).io.src_info := io.inst(i).src_info
// alu(i).io.hilo.rdata := hilo.rdata
// alu(i).io.mul.result := mul.result // alu(i).io.mul.result := mul.result
// alu(i).io.mul.ready := mul.ready // alu(i).io.mul.ready := mul.ready
// alu(i).io.div.ready := div.ready // alu(i).io.div.ready := div.ready
// alu(i).io.div.result := div.result // alu(i).io.div.result := div.result
// alu(i).io.csr_rdata := io.csr_rdata(i) alu(i).io.csr_rdata := io.csr_rdata(i)
// alu(i).io.llbit := io.llbit io.inst(i).ex.out := io.inst(i).ex.in
// io.inst(i).ex.out := io.inst(i).ex.in io.inst(i).ex.out.flush_req := io.inst(i).ex.in.flush_req
// io.inst(i).ex.out.flush_req := io.inst(i).ex.in.flush_req || alu(i).io.overflow io.inst(i).ex.out.excode := io.inst(i).ex.in.excode
// io.inst(i).ex.out.excode := MuxCase( }
// io.inst(i).ex.in.excode,
// Seq(
// (io.inst(i).ex.in.excode =/= EX_NO) -> io.inst(i).ex.in.excode,
// alu(i).io.overflow -> EX_OV,
// ),
// )
// }
// mul.src1 := Mux(io.inst(0).mul_en, io.inst(0).src_info.src1_data, io.inst(1).src_info.src1_data) // mul.src1 := Mux(io.inst(0).mul_en, io.inst(0).src_info.src1_data, io.inst(1).src_info.src1_data)
// mul.src2 := Mux(io.inst(0).mul_en, io.inst(0).src_info.src2_data, io.inst(1).src_info.src2_data) // mul.src2 := Mux(io.inst(0).mul_en, io.inst(0).src_info.src2_data, io.inst(1).src_info.src2_data)
@ -85,34 +72,12 @@
// io.stall_req := (io.inst.map(_.div_en).reduce(_ || _) && !div.ready) || // io.stall_req := (io.inst.map(_.div_en).reduce(_ || _) && !div.ready) ||
// (io.inst.map(_.mul_en).reduce(_ || _) && !mul.ready) // (io.inst.map(_.mul_en).reduce(_ || _) && !mul.ready)
io.stall_req := false.B
// io.inst(0).result := Mux( io.inst(0).result := Mux(
// io.inst(0).inst_info.branch_link, ALUOpType.isBru(io.inst(0).inst_info.op),
// io.inst(0).pc + 8.U, io.inst(0).pc + 4.U,
// alu(0).io.result, alu(0).io.result
// ) )
// io.inst(1).result := alu(1).io.result io.inst(1).result := alu(1).io.result
}
// hilo.wen := ((io.inst(1).hilo_wen && !io.inst.map(_.ex.out.flush_req).reduce(_ || _)) ||
// (io.inst(0).hilo_wen && !io.inst(0).ex.out.flush_req)) && io.ctrl.allow_to_go && !io.ctrl.do_flush
// hilo.wdata := Mux(io.inst(1).hilo_wen, alu(1).io.hilo.wdata, alu(0).io.hilo.wdata)
// llbit.do_flush := io.ctrl.eret
// llbit.wen := (io.inst(0).inst_info.op === EXE_LL || io.inst(0).inst_info.op === EXE_SC ||
// io.inst(1).inst_info.op === EXE_LL || io.inst(1).inst_info.op === EXE_SC) && io.ctrl.allow_to_go
// llbit.wdata := io.inst(0).inst_info.op === EXE_LL || io.inst(1).inst_info.op === EXE_LL
// val llbit_rdata = if (config.build) llbit.rdata else true.B
// io.llbit := llbit_rdata
// // ===----------------------------------------------------------------===
// // statistic
// // ===----------------------------------------------------------------===
// if (!config.build) {
// val branch_cnt = RegInit(0.U(32.W))
// val success_cnt = RegInit(0.U(32.W))
// when(io.branch.branch) { branch_cnt := branch_cnt + 1.U }
// when(!io.branch.pred_fail) { success_cnt := success_cnt + 1.U }
// io.statistic.get.branch := branch_cnt
// io.statistic.get.success := success_cnt
// }
// }

3
chisel/playground/test/src/TestMain.scala
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@ -7,10 +7,11 @@ import cache.ICache
import cpu.pipeline.fetch.BranchPredictorUnit import cpu.pipeline.fetch.BranchPredictorUnit
import cpu.pipeline.execute.Alu import cpu.pipeline.execute.Alu
import cpu.pipeline.execute.BranchCtrl import cpu.pipeline.execute.BranchCtrl
import cpu.pipeline.execute.Fu
object TestMain extends App { object TestMain extends App {
implicit val config = new CpuConfig() implicit val config = new CpuConfig()
def top = new BranchCtrl() def top = new Fu()
val useMFC = false // use MLIR-based firrtl compiler val useMFC = false // use MLIR-based firrtl compiler
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
if (useMFC) { if (useMFC) {