修改commit信号

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -62,6 +62,37 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   )
   dataMemoryAccess.dataMemory <> io.dataMemory
 
+  val csr_sel =
+    HasExcInt(io.writeBackStage.inst0.ex) || !HasExcInt(io.writeBackStage.inst1.ex)
+
+  io.csr.in.pc := MuxCase(
+    0.U,
+    Seq(
+      (io.ctrl.allow_to_go && csr_sel)  -> io.memoryStage.inst0.pc,
+      (io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst1.pc
+    )
+  )
+  io.csr.in.ex := MuxCase(
+    0.U.asTypeOf(new ExceptionInfo()),
+    Seq(
+      (io.ctrl.allow_to_go && csr_sel)  -> io.writeBackStage.inst0.ex,
+      (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.ex
+    )
+  )
+  io.csr.in.info := MuxCase(
+    0.U.asTypeOf(new InstInfo()),
+    Seq(
+      (io.ctrl.allow_to_go && csr_sel)  -> io.memoryStage.inst0.info,
+      (io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst1.info
+    )
+  )
+
+  io.csr.in.set_lr                       := dataMemoryAccess.memoryUnit.out.set_lr && io.ctrl.allow_to_go
+  io.csr.in.set_lr_val                   := dataMemoryAccess.memoryUnit.out.set_lr_val
+  io.csr.in.set_lr_addr                  := dataMemoryAccess.memoryUnit.out.set_lr_addr
+  dataMemoryAccess.memoryUnit.in.lr      := io.csr.out.lr
+  dataMemoryAccess.memoryUnit.in.lr_addr := io.csr.out.lr_addr
+
   io.decoderUnit(0).wen   := io.writeBackStage.inst0.info.reg_wen
   io.decoderUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
   io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
@@ -78,10 +109,11 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
     dataMemoryAccess.memoryUnit.out.ex,
     io.memoryStage.inst0.ex
   )
-  io.writeBackStage.inst0.commit := io.memoryStage.inst0.info.valid
 
-  io.writeBackStage.inst1.pc                        := io.memoryStage.inst1.pc
+  io.writeBackStage.inst1.pc   := io.memoryStage.inst1.pc
-  io.writeBackStage.inst1.info                      := io.memoryStage.inst1.info
+  io.writeBackStage.inst1.info := io.memoryStage.inst1.info
+  io.writeBackStage.inst1.info.valid := io.memoryStage.inst1.info.valid &&
+    !(io.fetchUnit.flush && csr_sel) // 指令0导致flush时，不应该提交指令1
   io.writeBackStage.inst1.rd_info.wdata             := io.memoryStage.inst1.rd_info.wdata
   io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
   io.writeBackStage.inst1.ex := Mux(
@@ -89,39 +121,6 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
     dataMemoryAccess.memoryUnit.out.ex,
     io.memoryStage.inst1.ex
   )
-  io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid &&
-    !(HasExcInt(io.writeBackStage.inst0.ex))
-
-  val csr_sel =
-    HasExcInt(io.writeBackStage.inst0.ex) || !HasExcInt(io.writeBackStage.inst1.ex)
-
-  io.csr.in.pc := MuxCase(
-    0.U,
-    Seq(
-      (io.ctrl.allow_to_go && csr_sel)  -> io.writeBackStage.inst0.pc,
-      (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.pc
-    )
-  )
-  io.csr.in.ex := MuxCase(
-    0.U.asTypeOf(new ExceptionInfo()),
-    Seq(
-      (io.ctrl.allow_to_go && csr_sel)  -> io.writeBackStage.inst0.ex,
-      (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.ex
-    )
-  )
-  io.csr.in.info := MuxCase(
-    0.U.asTypeOf(new InstInfo()),
-    Seq(
-      (io.ctrl.allow_to_go && csr_sel)  -> io.writeBackStage.inst0.info,
-      (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.info
-    )
-  )
-
-  io.csr.in.set_lr                       := dataMemoryAccess.memoryUnit.out.set_lr && io.ctrl.allow_to_go
-  io.csr.in.set_lr_val                   := dataMemoryAccess.memoryUnit.out.set_lr_val
-  io.csr.in.set_lr_addr                  := dataMemoryAccess.memoryUnit.out.set_lr_addr
-  dataMemoryAccess.memoryUnit.in.lr      := io.csr.out.lr
-  dataMemoryAccess.memoryUnit.in.lr_addr := io.csr.out.lr_addr
 
   io.ctrl.flush     := io.fetchUnit.flush
   io.ctrl.mem_stall := !dataMemoryAccess.memoryUnit.out.ready && dataMemoryAccess.memoryUnit.in.mem_en

chisel/playground/src/pipeline/writeback/WriteBackStage.scala

@@ -7,11 +7,10 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class MemWbInst extends Bundle {
-  val pc        = UInt(PC_WID.W)
+  val pc      = UInt(PC_WID.W)
-  val info = new InstInfo()
+  val info    = new InstInfo()
-  val rd_info   = new RdInfo()
+  val rd_info = new RdInfo()
-  val commit     = Bool()
+  val ex      = new ExceptionInfo()
-  val ex        = new ExceptionInfo()
 }
 
 class MemoryUnitWriteBackUnit extends Bundle {

chisel/playground/src/pipeline/writeback/WriteBackUnit.scala

@@ -15,13 +15,18 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
     val debug          = new DEBUG()
   })
 
-  io.regfile(0).wen := io.writeBackStage.inst0.info.reg_wen &&
+  io.regfile(0).wen :=
-    io.ctrl.allow_to_go && !(HasExcInt(io.writeBackStage.inst0.ex))
+    io.writeBackStage.inst0.info.valid &&
+      io.writeBackStage.inst0.info.reg_wen &&
+      io.ctrl.allow_to_go &&
+      !(HasExcInt(io.writeBackStage.inst0.ex))
   io.regfile(0).waddr := io.writeBackStage.inst0.info.reg_waddr
   io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
 
   io.regfile(1).wen :=
-    io.writeBackStage.inst1.info.reg_wen && io.ctrl.allow_to_go &&
+    io.writeBackStage.inst1.info.valid &&
+      io.writeBackStage.inst1.info.reg_wen &&
+      io.ctrl.allow_to_go &&
       !(HasExcInt(io.writeBackStage.inst0.ex)) &&
       !(HasExcInt(io.writeBackStage.inst1.ex))
   io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
@@ -30,11 +35,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
   if (config.hasCommitBuffer) {
     val buffer = Module(new CommitBuffer()).io
     buffer.enq(0).wb_pc       := io.writeBackStage.inst0.pc
-    buffer.enq(0).wb_rf_wen   := io.regfile(0).wen || io.writeBackStage.inst0.commit && io.ctrl.allow_to_go
+    buffer.enq(0).wb_rf_wen   := io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go
     buffer.enq(0).wb_rf_wnum  := io.regfile(0).waddr
     buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata
     buffer.enq(1).wb_pc       := io.writeBackStage.inst1.pc
-    buffer.enq(1).wb_rf_wen   := io.regfile(1).wen || io.writeBackStage.inst1.commit && io.ctrl.allow_to_go
+    buffer.enq(1).wb_rf_wen   := io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
     buffer.enq(1).wb_rf_wnum  := io.regfile(1).waddr
     buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata
     buffer.flush              := io.ctrl.do_flush