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fix: 修复tlb的2选1锁的逻辑

This commit is contained in:
Liphen 2024-01-17 15:05:38 +08:00
parent 21b73762a5
commit 8f9fe9362f
1 changed files with 15 additions and 19 deletions
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24
chisel/playground/src/cache/mmu/Tlb.scala vendored
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@ -120,14 +120,14 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
val ar_sel_lock = RegInit(false.B) val ar_sel_lock = RegInit(false.B)
val ar_sel_val = RegInit(false.B) val ar_sel_val = RegInit(false.B)
// 我们默认优先发送数据tlb的请求 // 我们默认优先发送数据tlb的请求
val ar_sel = Mux(ar_sel_lock, ar_sel_val, req_ptw(0) && !req_ptw(1)) val choose_icache = Mux(ar_sel_lock, ar_sel_val, req_ptw(0) && !req_ptw(1))
when(io.dcache.ptw.vpn.valid) {
when(io.dcache.ptw.vpn.ready) { when(io.dcache.ptw.vpn.ready) {
ar_sel_lock := false.B when(io.dcache.ptw.vpn.valid) {
}.otherwise {
ar_sel_lock := true.B ar_sel_lock := true.B
ar_sel_val := ar_sel ar_sel_val := choose_icache
}.otherwise {
ar_sel_lock := false.B
} }
} }
@ -139,9 +139,9 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
io.dcache.page_fault := dpage_fault io.dcache.page_fault := dpage_fault
// 将ptw模块集成到dcache中，ptw通过dcache的axi进行内存访问 // 将ptw模块集成到dcache中，ptw通过dcache的axi进行内存访问
io.dcache.ptw.vpn.valid := false.B io.dcache.ptw.vpn.valid := Mux(choose_icache, req_ptw(0), req_ptw(1))
io.dcache.ptw.access_type := Mux(ar_sel, AccessType.fetch, io.dcache.access_type) io.dcache.ptw.access_type := Mux(choose_icache, AccessType.fetch, io.dcache.access_type)
io.dcache.ptw.vpn.bits := Mux(ar_sel, ivpn, dvpn) io.dcache.ptw.vpn.bits := Mux(choose_icache, ivpn, dvpn)
io.dcache.ptw.pte.ready := true.B // 恒为true io.dcache.ptw.pte.ready := true.B // 恒为true
io.dcache.csr <> io.csr io.dcache.csr <> io.csr
@ -222,15 +222,13 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
itlb := tlbl2(PriorityEncoder(il2_hit_vec)) itlb := tlbl2(PriorityEncoder(il2_hit_vec))
}.otherwise { }.otherwise {
req_ptw(0) := true.B req_ptw(0) := true.B
when(ar_sel && io.dcache.ptw.vpn.ready) { when(choose_icache && io.dcache.ptw.vpn.ready) {
io.dcache.ptw.vpn.valid := true.B
immu_state := search_pte immu_state := search_pte
} }
} }
} }
is(search_pte) { is(search_pte) {
req_ptw(0) := true.B req_ptw(0) := true.B
io.dcache.ptw.vpn.valid := true.B
when(io.dcache.ptw.pte.valid) { when(io.dcache.ptw.pte.valid) {
when(io.dcache.ptw.pte.bits.access_fault) { when(io.dcache.ptw.pte.bits.access_fault) {
iaccess_fault := true.B iaccess_fault := true.B
@ -324,15 +322,13 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
dtlb := tlbl2(PriorityEncoder(dl2_hit_vec)) dtlb := tlbl2(PriorityEncoder(dl2_hit_vec))
}.otherwise { }.otherwise {
req_ptw(1) := true.B req_ptw(1) := true.B
when(!ar_sel && io.dcache.ptw.vpn.ready) { when(!choose_icache && io.dcache.ptw.vpn.ready) {
io.dcache.ptw.vpn.valid := true.B
dmmu_state := search_pte dmmu_state := search_pte
} }
} }
} }
is(search_pte) { is(search_pte) {
req_ptw(1) := true.B req_ptw(1) := true.B
io.dcache.ptw.vpn.valid := true.B
when(io.dcache.ptw.pte.valid) { when(io.dcache.ptw.pte.valid) {
when(io.dcache.ptw.pte.bits.access_fault) { when(io.dcache.ptw.pte.bits.access_fault) {
daccess_fault := true.B daccess_fault := true.B