完成对idu的修改
This commit is contained in:
parent
ec63ebc747
commit
8cc7e38b8b
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@ -8,10 +8,8 @@ import cpu.CpuConfig
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class ExceptionInfo extends Bundle {
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class ExceptionInfo extends Bundle {
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val flush_req = Bool()
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val flush_req = Bool()
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val eret = Bool()
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val excode = Vec(EXCODE_WID, Bool())
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val badvaddr = UInt(PC_WID.W)
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val int = Vec(INT_WID, Bool())
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val bd = Bool()
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// val excode = UInt(EXCODE_WID.W)
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}
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}
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class SrcInfo extends Bundle {
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class SrcInfo extends Bundle {
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@ -36,7 +34,6 @@ class InstInfo extends Bundle {
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val imm = UInt(XLEN.W)
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val imm = UInt(XLEN.W)
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val dual_issue = Bool()
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val dual_issue = Bool()
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val branch_link = Bool()
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val branch_link = Bool()
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val mem_addr = UInt(DATA_ADDR_WID.W)
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val inst = UInt(INST_WID.W)
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val inst = UInt(INST_WID.W)
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}
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}
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@ -17,6 +17,9 @@ trait Constants extends CoreParameter {
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def SINGLE_ISSUE = false.B
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def SINGLE_ISSUE = false.B
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def DUAL_ISSUE = true.B
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def DUAL_ISSUE = true.B
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def INT_WID = 12
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def EXCODE_WID = 16
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// div
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// div
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def DIV_CTRL_WID = 2
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def DIV_CTRL_WID = 2
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def DIV_FREE = 0.U(DIV_CTRL_WID.W)
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def DIV_FREE = 0.U(DIV_CTRL_WID.W)
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@ -94,7 +97,7 @@ trait AXIConst {
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def RESP_SLVERR = 2
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def RESP_SLVERR = 2
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def RESP_DECERR = 3
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def RESP_DECERR = 3
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}
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}
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object Const extends Constants with AXIConst
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object Const extends Constants with AXIConst with HasExceptionNO
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object Instructions extends HasInstrType with CoreParameter {
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object Instructions extends HasInstrType with CoreParameter {
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def NOP = 0x00000013.U
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def NOP = 0x00000013.U
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@ -173,6 +173,40 @@ object CSROpType {
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def clri = "b111".U
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def clri = "b111".U
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}
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}
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trait HasExceptionNO {
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def instrAddrMisaligned = 0
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def instrAccessFault = 1
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def illegalInstr = 2
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def breakPoint = 3
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def loadAddrMisaligned = 4
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def loadAccessFault = 5
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def storeAddrMisaligned = 6
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def storeAccessFault = 7
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def ecallU = 8
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def ecallS = 9
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def ecallM = 11
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def instrPageFault = 12
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def loadPageFault = 13
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def storePageFault = 15
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val ExcPriority = Seq(
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breakPoint, // TODO: different BP has different priority
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instrPageFault,
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instrAccessFault,
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illegalInstr,
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instrAddrMisaligned,
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ecallM,
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ecallS,
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ecallU,
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storeAddrMisaligned,
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loadAddrMisaligned,
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storePageFault,
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loadPageFault,
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storeAccessFault,
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loadAccessFault
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)
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}
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object Causes {
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object Causes {
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val misaligned_fetch = 0x0
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val misaligned_fetch = 0x0
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val fetch_access = 0x1
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val fetch_access = 0x1
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@ -13,7 +13,9 @@ class Decoder extends Module with HasInstrType {
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val inst = UInt(INST_WID.W)
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val inst = UInt(INST_WID.W)
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})
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})
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// outputs
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// outputs
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val out = Output(new InstInfo())
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val out = Output(new Bundle {
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val inst_info = new InstInfo()
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})
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})
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})
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val inst = io.in.inst
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val inst = io.in.inst
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@ -35,24 +37,24 @@ class Decoder extends Module with HasInstrType {
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val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
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val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
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io.out.inst_valid := instrType === InstrN
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io.out.inst_info.inst_valid := instrType === InstrN
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io.out.reg1_ren := src1Type === SrcType.reg
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io.out.inst_info.reg1_ren := src1Type === SrcType.reg
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io.out.reg1_raddr := rs
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io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U)
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io.out.reg2_ren := src2Type === SrcType.reg
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io.out.inst_info.reg2_ren := src2Type === SrcType.reg
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io.out.reg2_raddr := rt
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io.out.inst_info.reg2_raddr := Mux(src2Type === SrcType.reg, rt, 0.U)
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io.out.fusel := fuType
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io.out.inst_info.fusel := fuType
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io.out.op := fuOpType
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io.out.inst_info.op := fuOpType
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when(fuType === FuType.bru) {
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when(fuType === FuType.bru) {
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def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
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def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
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when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.op := ALUOpType.call }
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when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.inst_info.op := ALUOpType.call }
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when(fuOpType === ALUOpType.jalr) {
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when(fuOpType === ALUOpType.jalr) {
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when(isLink(rs)) { io.out.op := ALUOpType.ret }
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when(isLink(rs)) { io.out.inst_info.op := ALUOpType.ret }
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when(isLink(rd)) { io.out.op := ALUOpType.call }
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when(isLink(rd)) { io.out.inst_info.op := ALUOpType.call }
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}
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}
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}
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}
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io.out.reg_wen := isrfWen(instrType)
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io.out.inst_info.reg_wen := isrfWen(instrType)
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io.out.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
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io.out.inst_info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
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io.out.imm := LookupTree(
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io.out.inst_info.imm := LookupTree(
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instrType,
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instrType,
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Seq(
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Seq(
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InstrI -> signedExtend(inst(31, 20), XLEN),
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InstrI -> signedExtend(inst(31, 20), XLEN),
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@ -63,9 +65,7 @@ class Decoder extends Module with HasInstrType {
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InstrJ -> signedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
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InstrJ -> signedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
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)
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)
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)
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)
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// io.out.csr_addr := Cat(inst(15, 11), inst(2, 0))
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io.out.inst_info.dual_issue := false.B
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io.out.dual_issue := false.B
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io.out.inst_info.inst := inst
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io.out.inst := inst
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io.out.inst_info.branch_link := VecInit(ALUOpType.jal, ALUOpType.jalr).contains(fuOpType)
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io.out.branch_link := VecInit(ALUOpType.jal, ALUOpType.jalr).contains(fuOpType)
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io.out.mem_addr := DontCare
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}
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}
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@ -1,197 +1,159 @@
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// package cpu.pipeline.decoder
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package cpu.pipeline.decoder
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// import chisel3._
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import chisel3._
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// import chisel3.util._
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import chisel3.util._
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// import cpu.defines._
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import chisel3.util.experimental.BoringUtils
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// import cpu.defines.Const._
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import cpu.defines._
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// import cpu.{BranchPredictorConfig, CpuConfig}
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import cpu.defines.Const._
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// import cpu.pipeline.execute.DecoderUnitExecuteUnit
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import cpu.{BranchPredictorConfig, CpuConfig}
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// import cpu.pipeline.fetch.BufferUnit
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import cpu.pipeline.execute.DecoderUnitExecuteUnit
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import cpu.pipeline.fetch.BufferUnit
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// class InstFifoDecoderUnit(implicit val config: CpuConfig) extends Bundle {
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class InstFifoDecoderUnit(implicit val config: CpuConfig) extends Bundle {
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// val allow_to_go = Output(Vec(config.decoderNum, Bool()))
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val allow_to_go = Output(Vec(config.decoderNum, Bool()))
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// val inst = Input(Vec(config.decoderNum, new BufferUnit()))
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val inst = Input(Vec(config.decoderNum, new BufferUnit()))
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// val info = Input(new Bundle {
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val info = Input(new Bundle {
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// val empty = Bool()
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val empty = Bool()
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// val almost_empty = Bool()
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val almost_empty = Bool()
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// })
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})
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// }
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}
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// class DataForwardToDecoderUnit extends Bundle {
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class DataForwardToDecoderUnit extends Bundle {
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// val exe = new RegWrite()
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val exe = new RegWrite()
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// val mem_wreg = Bool()
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val mem_wreg = Bool()
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// val mem = new RegWrite()
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val mem = new RegWrite()
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// }
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}
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// class CsrDecoderUnit extends Bundle {
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class CsrDecoderUnit extends Bundle {
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// val access_allowed = Bool()
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val access_allowed = Bool()
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// val kernel_mode = Bool()
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val kernel_mode = Bool()
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// val intterupt_allowed = Bool()
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val intterupt_allowed = Bool()
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// val cause_ip = UInt(8.W)
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val cause_ip = UInt(8.W)
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// val status_im = UInt(8.W)
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val status_im = UInt(8.W)
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// }
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}
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// class DecoderUnit(implicit val config: CpuConfig) extends Module {
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class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExceptionNO {
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// val io = IO(new Bundle {
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val io = IO(new Bundle {
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// // 输入
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// 输入
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// val instFifo = new InstFifoDecoderUnit()
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val instFifo = new InstFifoDecoderUnit()
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// val regfile = Vec(config.decoderNum, new Src12Read())
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val regfile = Vec(config.decoderNum, new Src12Read())
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// val forward = Input(Vec(config.fuNum, new DataForwardToDecoderUnit()))
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val forward = Input(Vec(config.fuNum, new DataForwardToDecoderUnit()))
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// val csr = Input(new CsrDecoderUnit())
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val csr = Input(new CsrDecoderUnit())
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// // 输出
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// 输出
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// val fetchUnit = new Bundle {
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val fetchUnit = new Bundle {
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// val branch = Output(Bool())
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val branch = Output(Bool())
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// val target = Output(UInt(PC_WID.W))
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val target = Output(UInt(PC_WID.W))
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// }
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}
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// val bpu = new Bundle {
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val bpu = new Bundle {
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// val bpuConfig = new BranchPredictorConfig()
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val bpuConfig = new BranchPredictorConfig()
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// val pc = Output(UInt(PC_WID.W))
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val pc = Output(UInt(PC_WID.W))
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// val decoded_inst0 = Output(new InstInfo())
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val decoded_inst0 = Output(new InstInfo())
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// val id_allow_to_go = Output(Bool())
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val id_allow_to_go = Output(Bool())
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// val pht_index = Output(UInt(bpuConfig.phtDepth.W))
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val pht_index = Output(UInt(bpuConfig.phtDepth.W))
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// val branch_inst = Input(Bool())
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val branch_inst = Input(Bool())
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// val pred_branch = Input(Bool())
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val pred_branch = Input(Bool())
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// val branch_target = Input(UInt(PC_WID.W))
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val branch_target = Input(UInt(PC_WID.W))
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// val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
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val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
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// }
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}
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// val executeStage = Output(new DecoderUnitExecuteUnit())
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val executeStage = Output(new DecoderUnitExecuteUnit())
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// val ctrl = new DecoderUnitCtrl()
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val ctrl = new DecoderUnitCtrl()
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// })
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})
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// val issue = Module(new Issue()).io
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val issue = Module(new Issue()).io
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// val decoder = Seq.fill(config.decoderNum)(Module(new Decoder()))
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val decoder = Seq.fill(config.decoderNum)(Module(new Decoder()))
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// val jumpCtrl = Module(new JumpCtrl()).io
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val jumpCtrl = Module(new JumpCtrl()).io
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// val forwardCtrl = Module(new ForwardCtrl()).io
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val forwardCtrl = Module(new ForwardCtrl()).io
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// io.regfile(0).src1.raddr := decoder(0).io.out.reg1_raddr
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io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
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// io.regfile(0).src2.raddr := decoder(0).io.out.reg2_raddr
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io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
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// io.regfile(1).src1.raddr := decoder(1).io.out.reg1_raddr
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io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr
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// io.regfile(1).src2.raddr := decoder(1).io.out.reg2_raddr
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io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr
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// forwardCtrl.in.forward := io.forward
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forwardCtrl.in.forward := io.forward
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// forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
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forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
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// issue.allow_to_go := io.ctrl.allow_to_go
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issue.allow_to_go := io.ctrl.allow_to_go
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// issue.instFifo := io.instFifo.info
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issue.instFifo := io.instFifo.info
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// jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
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jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
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// jumpCtrl.in.decoded_inst0 := decoder(0).io.out
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jumpCtrl.in.decoded_inst0 := decoder(0).io.out
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// jumpCtrl.in.forward := io.forward
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jumpCtrl.in.forward := io.forward
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// jumpCtrl.in.pc := io.instFifo.inst(0).pc
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jumpCtrl.in.pc := io.instFifo.inst(0).pc
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// jumpCtrl.in.reg1_data := io.regfile(0).src1.rdata
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jumpCtrl.in.reg1_data := io.regfile(0).src1.rdata
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// val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch
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val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch
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// io.fetchUnit.branch := inst0_branch
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io.fetchUnit.branch := inst0_branch
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// io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target)
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io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target)
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// io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
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io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
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// io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
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io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
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// io.bpu.id_allow_to_go := io.ctrl.allow_to_go
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io.bpu.id_allow_to_go := io.ctrl.allow_to_go
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// io.bpu.pc := io.instFifo.inst(0).pc
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io.bpu.pc := io.instFifo.inst(0).pc
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// io.bpu.decoded_inst0 := decoder(0).io.out
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io.bpu.decoded_inst0 := decoder(0).io.out
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// io.bpu.pht_index := io.instFifo.inst(0).pht_index
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io.bpu.pht_index := io.instFifo.inst(0).pht_index
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// io.ctrl.inst0.src1.ren := decoder(0).io.out.reg1_ren
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io.ctrl.inst0.src1.ren := decoder(0).io.out.inst_info.reg1_ren
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// io.ctrl.inst0.src1.raddr := decoder(0).io.out.reg1_raddr
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io.ctrl.inst0.src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
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// io.ctrl.inst0.src2.ren := decoder(0).io.out.reg2_ren
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io.ctrl.inst0.src2.ren := decoder(0).io.out.inst_info.reg2_ren
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// io.ctrl.inst0.src2.raddr := decoder(0).io.out.reg2_raddr
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io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
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// io.ctrl.branch := inst0_branch
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io.ctrl.branch := inst0_branch
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// val pc = io.instFifo.inst.map(_.pc)
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val pc = io.instFifo.inst.map(_.pc)
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// val inst = io.instFifo.inst.map(_.inst)
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val inst = io.instFifo.inst.map(_.inst)
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// val inst_info = decoder.map(_.io.out)
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val inst_info = decoder.map(_.io.out.inst_info)
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// val interrupt = io.csr.intterupt_allowed && (io.csr.cause_ip & io.csr.status_im).orR && !io.instFifo.info.empty
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// for (i <- 0 until (config.decoderNum)) {
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for (i <- 0 until (config.decoderNum)) {
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// decoder(i).io.in.inst := inst(i)
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decoder(i).io.in.inst := inst(i)
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// issue.decodeInst(i) := inst_info(i)
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issue.decodeInst(i) := inst_info(i)
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// issue.execute(i).mem_wreg := io.forward(i).mem_wreg
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issue.execute(i).mem_wreg := io.forward(i).mem_wreg
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// issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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// }
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}
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// io.executeStage.inst0.pc := pc(0)
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val int = WireInit(0.U(INT_WID.W))
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// io.executeStage.inst0.inst_info := inst_info(0)
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BoringUtils.addSink(int, "intDecoderUnit")
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// io.executeStage.inst0.inst_info.reg_wen := MuxLookup(inst_info(0).op, inst_info(0).reg_wen)(
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io.executeStage.inst0.ex.int.zip(int.asBools).map { case (x, y) => x := y }
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// Seq(
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val hasInt = int.orR
|
||||||
// EXE_MOVN -> (io.executeStage.inst0.src_info.src2_data =/= 0.U),
|
|
||||||
// EXE_MOVZ -> (io.executeStage.inst0.src_info.src2_data === 0.U)
|
|
||||||
// )
|
|
||||||
// )
|
|
||||||
// io.executeStage.inst0.inst_info.mem_addr :=
|
|
||||||
// io.executeStage.inst0.src_info.src1_data + Util.signedExtend(io.executeStage.inst0.inst_info.inst(15, 0))
|
|
||||||
// io.executeStage.inst0.src_info.src1_data := Mux(
|
|
||||||
// inst_info(0).reg1_ren,
|
|
||||||
// forwardCtrl.out.inst(0).src1.rdata,
|
|
||||||
// decoder(0).io.out.imm
|
|
||||||
// )
|
|
||||||
// io.executeStage.inst0.src_info.src2_data := Mux(
|
|
||||||
// inst_info(0).reg2_ren,
|
|
||||||
// forwardCtrl.out.inst(0).src2.rdata,
|
|
||||||
// decoder(0).io.out.imm
|
|
||||||
// )
|
|
||||||
// io.executeStage.inst0.ex.flush_req :=
|
|
||||||
// io.executeStage.inst0.ex.excode =/= EX_NO ||
|
|
||||||
// io.executeStage.inst0.ex.eret
|
|
||||||
// io.executeStage.inst0.ex.eret := inst_info(0).op === EXE_ERET
|
|
||||||
// io.executeStage.inst0.ex.badvaddr := pc(0)
|
|
||||||
// val inst0_ex_cpu =
|
|
||||||
// !io.csr.access_allowed && VecInit(EXE_MFC0, EXE_MTC0, EXE_TLBR, EXE_TLBWI, EXE_TLBWR, EXE_TLBP, EXE_ERET, EXE_WAIT)
|
|
||||||
// .contains(inst_info(0).op)
|
|
||||||
// io.executeStage.inst0.ex.excode := MuxCase(
|
|
||||||
// EX_NO,
|
|
||||||
// Seq(
|
|
||||||
// interrupt -> EX_INT,
|
|
||||||
// (pc(0)(1, 0).orR || (pc(0)(31) && !io.csr.kernel_mode)) -> EX_ADEL,
|
|
||||||
// (inst_info(0).inst_valid === INST_INVALID) -> EX_RI,
|
|
||||||
// (inst_info(0).op === EXE_SYSCALL) -> EX_SYS,
|
|
||||||
// (inst_info(0).op === EXE_BREAK) -> EX_BP,
|
|
||||||
// (inst0_ex_cpu) -> EX_CPU
|
|
||||||
// )
|
|
||||||
// )
|
|
||||||
// io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
|
|
||||||
// io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst
|
|
||||||
// io.executeStage.inst0.jb_info.pred_branch := io.bpu.pred_branch
|
|
||||||
// io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
|
|
||||||
// io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
|
|
||||||
|
|
||||||
// io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
|
io.executeStage.inst0.pc := pc(0)
|
||||||
// io.executeStage.inst1.pc := pc(1)
|
io.executeStage.inst0.inst_info := inst_info(0)
|
||||||
// io.executeStage.inst1.inst_info := inst_info(1)
|
io.executeStage.inst0.src_info.src1_data := Mux(
|
||||||
// io.executeStage.inst1.inst_info.reg_wen := MuxLookup(inst_info(1).op, inst_info(1).reg_wen)(
|
inst_info(0).reg1_ren,
|
||||||
// Seq(
|
forwardCtrl.out.inst(0).src1.rdata,
|
||||||
// EXE_MOVN -> (io.executeStage.inst1.src_info.src2_data =/= 0.U),
|
Util.signedExtend(pc(0), INST_ADDR_WID)
|
||||||
// EXE_MOVZ -> (io.executeStage.inst1.src_info.src2_data === 0.U)
|
)
|
||||||
// )
|
io.executeStage.inst0.src_info.src2_data := Mux(
|
||||||
// )
|
inst_info(0).reg2_ren,
|
||||||
// io.executeStage.inst1.inst_info.mem_addr :=
|
forwardCtrl.out.inst(0).src2.rdata,
|
||||||
// io.executeStage.inst1.src_info.src1_data + Util.signedExtend(io.executeStage.inst1.inst_info.inst(15, 0))
|
decoder(0).io.out.inst_info.imm
|
||||||
// io.executeStage.inst1.src_info.src1_data := Mux(
|
)
|
||||||
// inst_info(1).reg1_ren,
|
io.executeStage.inst0.ex.flush_req := io.executeStage.inst0.ex.excode.asUInt.orR
|
||||||
// forwardCtrl.out.inst(1).src1.rdata,
|
io.executeStage.inst0.ex.excode.map(_ := false.B)
|
||||||
// decoder(1).io.out.imm
|
io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid &&
|
||||||
// )
|
!hasInt && !io.instFifo.info.empty
|
||||||
// io.executeStage.inst1.src_info.src2_data := Mux(
|
|
||||||
// inst_info(1).reg2_ren,
|
io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
|
||||||
// forwardCtrl.out.inst(1).src2.rdata,
|
io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst
|
||||||
// decoder(1).io.out.imm
|
io.executeStage.inst0.jb_info.pred_branch := io.bpu.pred_branch
|
||||||
// )
|
io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
|
||||||
// io.executeStage.inst1.ex.flush_req := io.executeStage.inst1.ex.excode =/= EX_NO
|
io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
|
||||||
// io.executeStage.inst1.ex.eret := inst_info(1).op === EXE_ERET
|
|
||||||
// io.executeStage.inst1.ex.badvaddr := pc(1)
|
io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
|
||||||
// val inst1_ex_cpu =
|
io.executeStage.inst1.pc := pc(1)
|
||||||
// !io.csr.access_allowed && VecInit(EXE_MFC0, EXE_MTC0, EXE_TLBR, EXE_TLBWI, EXE_TLBWR, EXE_TLBP, EXE_ERET, EXE_WAIT)
|
io.executeStage.inst1.inst_info := inst_info(1)
|
||||||
// .contains(inst_info(1).op)
|
io.executeStage.inst1.src_info.src1_data := Mux(
|
||||||
// io.executeStage.inst1.ex.excode := MuxCase(
|
inst_info(1).reg1_ren,
|
||||||
// EX_NO,
|
forwardCtrl.out.inst(1).src1.rdata,
|
||||||
// Seq(
|
Util.signedExtend(pc(1), INST_ADDR_WID)
|
||||||
// (pc(1)(1, 0).orR || (pc(1)(31) && !io.csr.kernel_mode)) -> EX_ADEL,
|
)
|
||||||
// (inst_info(1).inst_valid === INST_INVALID) -> EX_RI,
|
io.executeStage.inst1.src_info.src2_data := Mux(
|
||||||
// (inst_info(1).op === EXE_SYSCALL) -> EX_SYS,
|
inst_info(1).reg2_ren,
|
||||||
// (inst_info(1).op === EXE_BREAK) -> EX_BP,
|
forwardCtrl.out.inst(1).src2.rdata,
|
||||||
// (inst1_ex_cpu) -> EX_CPU
|
decoder(1).io.out.inst_info.imm
|
||||||
// )
|
)
|
||||||
// )
|
io.executeStage.inst1.ex.excode.map(_ := false.B)
|
||||||
// }
|
io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
|
||||||
|
!hasInt && !io.instFifo.info.almost_empty
|
||||||
|
}
|
||||||
|
|
Loading…
Reference in New Issue