feat(csr): 增加s模式的csr
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Liphen
parent
d9f73ff104
commit
895f1e2697
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@ -1 +1 @@
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Subproject commit c84c78ef6d672f45c5da7f08328db45ad0e4f8fb
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Subproject commit e89bb7ff9246a977b7e7ded2b611739e1246d33d
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@ -10,7 +10,7 @@ case class CpuConfig(
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val hasMExtension: Boolean = true, // 是否有乘除法单元
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val hasAExtension: Boolean = true, // 是否有原子指令
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// 特权模式
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val hasSMode: Boolean = false, // 是否有S模式
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val hasSMode: Boolean = true, // 是否有S模式
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val hasUMode: Boolean = true, // 是否有U模式
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// 模块配置
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val hasCommitBuffer: Boolean = true, // 是否有提交缓存
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@ -107,7 +107,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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val dirty = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B)))))
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val lru = RegInit(VecInit(Seq.fill(nindex)(false.B))) // TODO:支持更多路数，目前只支持2路
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// 0:第0路脏位为真，1:第1路脏位为真，2:两路都为假
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// 对于2路组相连的cache: 0:第0路脏位为真，1:第1路脏位为真，2:两路都为假
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val dirty_table = Wire(Vec(nindex, UInt(log2Ceil(nway + 1).W)))
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// 用于指示哪个行的脏位为真
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val dirty_index = Wire(UInt(indexWidth.W))
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@ -53,11 +53,13 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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})
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/* CSR寄存器定义 */
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val mvendorid = RegInit(0.U(XLEN.W)) // 厂商ID
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val marchid = RegInit(0.U(XLEN.W)) // 架构ID
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val mimpid = RegInit(0.U(XLEN.W)) // 实现ID
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val mhartid = RegInit(0.U(XLEN.W)) // 硬件线程ID
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val mconfigptr = RegInit(0.U(XLEN.W)) // 配置寄存器指针
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// Machine Information Registers
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val mvendorid = RegInit(UInt(XLEN.W), 0.U) // 厂商ID
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val marchid = RegInit(UInt(XLEN.W), 0.U) // 架构ID
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val mimpid = RegInit(UInt(XLEN.W), 0.U) // 实现ID
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val mhartid = RegInit(UInt(XLEN.W), 0.U) // 硬件线程ID
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// Machine Trap Setup
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val mstatus_init = Wire(new Mstatus())
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mstatus_init := 0.U.asTypeOf(new Mstatus())
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mstatus_init.uxl := 2.U
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@ -73,37 +75,65 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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if (config.hasUMode) { extensions = extensions :+ 'u' }
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misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i))
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val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器
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val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器
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val mtvec = RegInit(0.U(XLEN.W)) // 中断向量基址寄存器
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val mcounteren = RegInit(0.U(XLEN.W)) // 计数器使能寄存器
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val mscratch = RegInit(0.U(XLEN.W)) // 临时寄存器
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val mepc = RegInit(0.U(XLEN.W)) // 异常程序计数器
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val mcause = RegInit(0.U(XLEN.W)) // 异常原因寄存器
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val mtval = RegInit(0.U(XLEN.W)) // 异常值寄存器
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val medeleg = RegInit(UInt(XLEN.W), 0.U) // 异常代理寄存器
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val mideleg = RegInit(UInt(XLEN.W), 0.U) // 中断代理寄存器
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val mie = RegInit(UInt(XLEN.W), 0.U) // 中断使能寄存器
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val mtvec = RegInit(UInt(XLEN.W), 0.U) // 中断向量基址寄存器
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val mcounteren = RegInit(UInt(XLEN.W), 0.U) // 计数器使能寄存器
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// Machine Trap Handling
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val mscratch = RegInit(UInt(XLEN.W), 0.U) // 临时寄存器
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val mepc = RegInit(UInt(XLEN.W), 0.U) // 异常程序计数器
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val mcause = RegInit(UInt(XLEN.W), 0.U) // 异常原因寄存器
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val mtval = RegInit(UInt(XLEN.W), 0.U) // 异常值寄存器
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val mipWire = WireInit(0.U.asTypeOf(new Interrupt))
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val mipReg = RegInit(0.U(64.W))
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val mipFixMask = "h77f".U(64.W)
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val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt) // 中断挂起寄存器
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val mcycle = RegInit(0.U(XLEN.W)) // 时钟周期计数器
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mcycle := mcycle + 1.U
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val minstret = RegInit(0.U(XLEN.W)) // 指令计数器
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val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器
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val tdata1 = RegInit(0.U(XLEN.W)) // 跟踪寄存器数据1寄存器
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// Machine Memory Protection
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val pmpcfg0 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg1 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg2 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg3 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr0 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr1 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr2 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr3 = RegInit(UInt(XLEN.W), 0.U)
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// 仅供调试使用
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val satp = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg0 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg1 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg2 = RegInit(UInt(XLEN.W), 0.U)
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val pmpcfg3 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr0 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr1 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr2 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddr3 = RegInit(UInt(XLEN.W), 0.U)
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val pmpaddrWmask = "h3fffffff".U(64.W) // 32bit physical address
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// Machine Counter/Timers
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val mcycle = RegInit(UInt(XLEN.W), 0.U) // 时钟周期计数器
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mcycle := mcycle + 1.U
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val minstret = RegInit(UInt(XLEN.W), 0.U) // 指令计数器
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// Supervisor Trap Setup
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// sstatus 状态寄存器，源自mstatus
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val sstatusWmask = "hc6122".U(XLEN.W)
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val sstatusRmask = sstatusWmask | "h8000000300018000".U
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// sedeleg 异常代理寄存器，未实现
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// sideleg 中断代理寄存器，未实现
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// sie 中断使能寄存器，源自mie
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val sieMask = "h222".U(64.W) & mideleg
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val stvec = RegInit(UInt(XLEN.W), 0.U) // 中断向量基址寄存器
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val scounteren = RegInit(UInt(XLEN.W), 0.U) // 计数器使能寄存器
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// Supervisor Trap Handling
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val sscratch = RegInit(UInt(XLEN.W), 0.U) // 临时寄存器
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val sepc = RegInit(UInt(XLEN.W), 0.U) // 异常程序计数器
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val scause = RegInit(UInt(XLEN.W), 0.U) // 异常原因寄存器
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val stval = RegInit(UInt(XLEN.W), 0.U) // 异常值寄存器
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// sip 中断挂起寄存器，源自mip
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val sipMask = "h222".U(64.W) & mideleg
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// Supervisor Protection and Translation
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val satp = RegInit(UInt(XLEN.W), 0.U) // 页表基址寄存器
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// Debug/Trace Registers (shared with Debug Mode)
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val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器
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val tdata1 = RegInit(UInt(XLEN.W), 0.U) // 跟踪寄存器数据1寄存器
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val rdata = Wire(UInt(XLEN.W))
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val wdata = Wire(UInt(XLEN.W))
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@ -132,47 +162,26 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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}
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val mstatus_wmask = Mux(
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wdata.asTypeOf(new Mstatus).mpp === ModeM || wdata.asTypeOf(new Mstatus).mpp === ModeU,
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VecInit(ModeM, ModeS, ModeU).contains(wdata.asTypeOf(new Mstatus).mpp),
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"h0000000000021888".U(64.W),
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"h0000000000020088".U(64.W)
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)
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// CSR reg map
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val mapping = Map(
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// User Trap Setup
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// MaskedRegMap(Ustatus, ustatus),
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// MaskedRegMap(Uie, uie, 0.U, MaskedRegMap.Unwritable),
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// MaskedRegMap(Utvec, utvec),
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// User Trap Handling
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// MaskedRegMap(Uscratch, uscratch),
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// MaskedRegMap(Uepc, uepc),
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// MaskedRegMap(Ucause, ucause),
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// MaskedRegMap(Utval, utval),
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// MaskedRegMap(Uip, uip),
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// User Floating-Point CSRs (not implemented)
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// MaskedRegMap(Fflags, fflags),
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// MaskedRegMap(Frm, frm),
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// MaskedRegMap(Fcsr, fcsr),
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// User Counter/Timers
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MaskedRegMap(Cycle, mcycle),
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// MaskedRegMap(Time, time),
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// MaskedRegMap(Instret, minstret),
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// // Supervisor Trap Setup TODO
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// MaskedRegMap(Sstatus, mstatus, sstatusWmask, mstatusUpdateSideEffect, sstatusRmask),
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// // MaskedRegMap(Sedeleg, Sedeleg),
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// // MaskedRegMap(Sideleg, Sideleg),
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// MaskedRegMap(Sie, mie, sieMask, MaskedRegMap.NoSideEffect, sieMask),
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// MaskedRegMap(Stvec, stvec),
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// MaskedRegMap(Scounteren, scounteren),
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// // Supervisor Trap Handling
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// MaskedRegMap(Sscratch, sscratch),
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// MaskedRegMap(Sepc, sepc),
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// MaskedRegMap(Scause, scause),
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// MaskedRegMap(Stval, stval),
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// MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
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// Supervisor Trap Setup
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MaskedRegMap(Sstatus, mstatus, sstatusWmask, mstatusUpdateSideEffect, sstatusRmask),
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MaskedRegMap(Sie, mie, sieMask, MaskedRegMap.NoSideEffect, sieMask),
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MaskedRegMap(Stvec, stvec),
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MaskedRegMap(Scounteren, scounteren),
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// Supervisor Trap Handling
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MaskedRegMap(Sscratch, sscratch),
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MaskedRegMap(Sepc, sepc),
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MaskedRegMap(Scause, scause),
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MaskedRegMap(Stval, stval),
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MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
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// Supervisor Protection and Translation
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MaskedRegMap(Satp, satp),
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// Machine Information Registers
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@ -182,9 +191,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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MaskedRegMap(Mhartid, mhartid, 0.U, MaskedRegMap.Unwritable),
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// Machine Trap Setup
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MaskedRegMap(Mstatus, mstatus, mstatus_wmask),
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MaskedRegMap(Misa, misa), // now MXL, EXT is not changeable
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// MaskedRegMap(Medeleg, medeleg, "hbbff".U(64.W)), TODO
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// MaskedRegMap(Mideleg, mideleg, "h222".U(64.W)),
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MaskedRegMap(Misa, misa), // MXL，EXT目前不支持可变
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MaskedRegMap(Medeleg, medeleg, "hbbff".U(XLEN.W)),
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MaskedRegMap(Mideleg, mideleg, "h222".U(XLEN.W)),
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MaskedRegMap(Mie, mie),
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MaskedRegMap(Mtvec, mtvec),
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MaskedRegMap(Mcounteren, mcounteren),
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@ -207,7 +216,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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// Debug/Trace Registers (shared with Debug Mode)
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MaskedRegMap(Tselect, tselect, 0.U, MaskedRegMap.Unwritable), // 用于通过 risc-v test
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MaskedRegMap(Tdata1, tdata1, 0.U, MaskedRegMap.Unwritable)
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) //++ perfCntsLoMapping
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)
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val mode = RegInit(Priv.m) // 当前特权模式
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@ -271,8 +280,8 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val illegal_addr = MaskedRegMap.isIllegalAddr(mapping, addr)
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// Fix Mip/Sip write
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val fixMapping = Map(
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MaskedRegMap(Mip, mipReg.asUInt, mipFixMask)
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// MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) //TODO：增加sip
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MaskedRegMap(Mip, mipReg.asUInt, mipFixMask),
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MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask)
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)
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val rdataDummy = Wire(UInt(XLEN.W))
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MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen, wdata)
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@ -346,7 +355,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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when(isMret) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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// mstatusNew.mpp.m := ModeU //TODO: add mode U
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// mstatusNew.mpp.m := ModeU
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mstatusNew.ie.m := mstatusOld.pie.m
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mode := mstatusOld.mpp
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mstatusNew.pie.m := true.B
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@ -356,6 +365,31 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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ret_target := mepc(VADDR_WID - 1, 0)
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}
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when(isSret) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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// mstatusNew.mpp.m := ModeU
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mstatusNew.ie.s := mstatusOld.pie.s
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mode := Cat(0.U(1.W), mstatusOld.spp)
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mstatusNew.pie.s := true.B
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mstatusNew.spp := ModeU
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mstatus := mstatusNew.asUInt
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lr := false.B
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ret_target := sepc(VADDR_WID - 1, 0)
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}
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//TODO: add mode U
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// when (isUret) {
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// val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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// val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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// // mstatusNew.mpp.m := ModeU
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// mstatusNew.ie.u := mstatusOld.pie.u
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// mode := ModeU
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// mstatusNew.pie.u := true.B
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// mstatus := mstatusNew.asUInt
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// ret_target := uepc(VADDR_WID-1, 0)
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// }
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io.decoderUnit.mode := mode
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io.executeUnit.out.ex := io.executeUnit.in.ex
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io.executeUnit.out.ex.exception(illegalInstr) :=
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