diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index 8c680cd..a4e2ad9 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -34,12 +34,8 @@ class Fu(implicit val config: CpuConfig) extends Module {
 
   val alu        = Seq.fill(config.decoderNum)(Module(new Alu()))
   val branchCtrl = Module(new BranchCtrl()).io
-  val mou        = Module(new Mou()).io
   val mdu        = Module(new Mdu()).io
 
-  mou.in.info := io.inst(0).info
-  mou.in.pc   := io.inst(0).pc
-
   branchCtrl.in.pc            := io.inst(0).pc
   branchCtrl.in.info          := io.inst(0).info
   branchCtrl.in.src_info      := io.inst(0).src_info
@@ -49,8 +45,8 @@ class Fu(implicit val config: CpuConfig) extends Module {
   io.branch.branch            := branchCtrl.out.branch
 
   val branchCtrl_flush = (branchCtrl.out.pred_fail || io.branch.jump_regiser)
-  io.branch.flush  := branchCtrl_flush || mou.out.flush
-  io.branch.target := Mux(branchCtrl_flush, branchCtrl.out.target, mou.out.target)
+  io.branch.flush  := branchCtrl_flush
+  io.branch.target := branchCtrl.out.target
 
   for (i <- 0 until (config.fuNum)) {
     alu(i).io.info     := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new InstInfo()))
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index 0547ce9..fef9b28 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -24,6 +24,11 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   })
 
   val dataMemoryAccess = Module(new DataMemoryAccess()).io
+  val mou              = Module(new Mou()).io
+
+  mou.in.info := io.memoryStage.inst0.info
+  mou.in.pc   := io.memoryStage.inst0.pc
+
   dataMemoryAccess.memoryUnit.in.allow_to_go := io.ctrl.allow_to_go
   val mem_sel = VecInit(
     io.memoryStage.inst0.info.valid &&
@@ -108,9 +113,9 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   dataMemoryAccess.memoryUnit.in.lr      := io.csr.out.lr
   dataMemoryAccess.memoryUnit.in.lr_addr := io.csr.out.lr_addr
 
-  io.fetchUnit.flush  := io.csr.out.flush && io.ctrl.allow_to_go
-  io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
-
   io.ctrl.flush     := io.fetchUnit.flush
   io.ctrl.mem_stall := !dataMemoryAccess.memoryUnit.out.ready && dataMemoryAccess.memoryUnit.in.mem_en
+
+  io.fetchUnit.flush  := io.ctrl.allow_to_go && (io.csr.out.flush || mou.out.flush)
+  io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.flush_pc, mou.out.target)
 }
diff --git a/chisel/playground/src/pipeline/execute/Mou.scala b/chisel/playground/src/pipeline/memory/Mou.scala
similarity index 95%
rename from chisel/playground/src/pipeline/execute/Mou.scala
rename to chisel/playground/src/pipeline/memory/Mou.scala
index e73f723..c7962eb 100644
--- a/chisel/playground/src/pipeline/execute/Mou.scala
+++ b/chisel/playground/src/pipeline/memory/Mou.scala
@@ -1,4 +1,4 @@
-package cpu.pipeline.execute
+package cpu.pipeline.memory
 
 import chisel3._
 import chisel3.util._