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修改信号名

This commit is contained in:
Liphen 2023-11-26 11:29:59 +08:00
parent 68055ff745
commit 7daed5b3a5
3 changed files with 16 additions and 16 deletions
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8
chisel/playground/src/Core.scala
View File

@ -50,7 +50,7 @@ class Core(implicit val config: CpuConfig) extends Module {
fetchUnit.execute <> executeUnit.fetchUnit
fetchUnit.decoder <> decoderUnit.fetchUnit
fetchUnit.instFifo.full := instFifo.full
fetchUnit.iCache.inst_valid := io.inst.valid
fetchUnit.iCache.inst_valid := io.inst.inst_valid
io.inst.addr(0) := fetchUnit.iCache.pc
io.inst.addr(1) := fetchUnit.iCache.pc_next
for (i <- 2 until config.instFetchNum) {
@ -80,9 +80,9 @@ class Core(implicit val config: CpuConfig) extends Module {
for (i <- 0 until config.instFetchNum) {
instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
bpu.instBuffer.pc(i) := instFifo.write(i).pc
instFifo.wen(i) := io.inst.valid(i)
instFifo.wen(i) := io.inst.inst_valid(i)
instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U
instFifo.write(i).inst := io.inst.rdata(i)
instFifo.write(i).inst := io.inst.inst(i)
instFifo.write(i).acc_err := io.inst.acc_err
instFifo.write(i).addr_err := io.inst.addr_err
}
@ -142,7 +142,7 @@ class Core(implicit val config: CpuConfig) extends Module {
executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei
io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
io.inst.en := !instFifo.full && !reset.asBool
io.inst.req := !instFifo.full && !reset.asBool
io.inst.ready := ctrl.fetchUnit.allow_to_go
io.data.ready := ctrl.memoryUnit.allow_to_go
}

10
chisel/playground/src/cache/ICache.scala vendored
View File

@ -17,7 +17,7 @@ class ICache(implicit config: CpuConfig) extends Module {
val s_idle :: s_read :: s_finishwait :: Nil = Enum(3)
val status = RegInit(s_idle)
io.cpu.valid.map(_ := status === s_finishwait)
io.cpu.inst_valid.map(_ := status === s_finishwait)
val read_next_addr = (status === s_idle || status === s_finishwait)
io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR
val addr_err = io.cpu.addr(read_next_addr)(63, 32).orR
@ -40,14 +40,14 @@ class ICache(implicit config: CpuConfig) extends Module {
io.axi.ar.prot := 0.U
io.axi.ar.cache := 0.U
io.axi.r.ready := true.B
io.cpu.rdata.map(_ := 0.U)
io.cpu.inst.map(_ := 0.U)
io.cpu.acc_err := acc_err
io.cpu.stall := false.B
io.cpu.rdata := rdata
io.cpu.inst := rdata
switch(status) {
is(s_idle) {
when(io.cpu.en) {
when(io.cpu.req) {
when(addr_err) {
acc_err := true.B
status := s_finishwait
@ -72,7 +72,7 @@ class ICache(implicit config: CpuConfig) extends Module {
is(s_finishwait) {
when(io.cpu.ready) {
acc_err := false.B
when(io.cpu.en) {
when(io.cpu.req) {
when(addr_err) {
acc_err := true.B
status := s_finishwait

14
chisel/playground/src/defines/Bundles.scala
View File

@ -108,17 +108,17 @@ class WriteBackCtrl extends Bundle {
// cpu to icache
class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// read inst request from cpu
val en = Output(Bool())
val ready = Output(Bool())
val req = Output(Bool())
val ready = Output(Bool()) // !cpu_stall
val addr = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
val fence_i = Output(Bool())
// read inst result
val rdata = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
val valid = Input(Vec(config.instFetchNum, Bool()))
val acc_err = Input(Bool())
val addr_err = Input(Bool())
val stall = Input(Bool())
val inst = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
val inst_valid = Input(Vec(config.instFetchNum, Bool()))
val acc_err = Input(Bool())
val addr_err = Input(Bool())
val stall = Input(Bool()) // icache_stall
}
// cpu to dcache