diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index a73531b..19d095c 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -14,7 +14,7 @@ import pipeline.writeback._
 import ctrl._
 import cache.mmu._
 
-class Core(implicit val config: CpuConfig) extends Module {
+class Core(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ext_int = Input(new ExtInterrupt())
     val inst    = new Cache_ICache()
@@ -57,7 +57,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   fetchUnit.iCache.inst_valid := io.inst.inst_valid
   io.inst.addr(0)             := fetchUnit.iCache.pc
   io.inst.addr(1)             := fetchUnit.iCache.pc_next
-  for (i <- 2 until config.instFetchNum) {
+  for (i <- 2 until cpuConfig.instFetchNum) {
     io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U
   }
 
@@ -68,7 +68,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   instFifo.ren <> decoderUnit.instFifo.allow_to_go
   decoderUnit.instFifo.inst <> instFifo.read
 
-  for (i <- 0 until config.instFetchNum) {
+  for (i <- 0 until cpuConfig.instFetchNum) {
     instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
     bpu.instBuffer.pc(i)        := instFifo.write(i).pc
     instFifo.wen(i)             := io.inst.inst_valid(i)
@@ -80,7 +80,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   decoderUnit.instFifo.info.empty        := instFifo.empty
   decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty
   decoderUnit.regfile <> regfile.read
-  for (i <- 0 until (config.commitNum)) {
+  for (i <- 0 until (cpuConfig.commitNum)) {
     decoderUnit.forward(i).exe      := executeUnit.decoderUnit.forward(i).exe
     decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg
     decoderUnit.forward(i).mem      := memoryUnit.decoderUnit(i)
diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala
index 8f4836c..01ba764 100644
--- a/chisel/playground/src/CpuConfig.scala
+++ b/chisel/playground/src/CpuConfig.scala
@@ -2,6 +2,7 @@ package cpu
 
 import chisel3.util._
 import cpu.defines.Const._
+import cpu.defines.Sv39Const
 
 case class CpuConfig(
   val build: Boolean = false, // 是否为build模式
@@ -29,33 +30,29 @@ case class BranchPredictorConfig(
 
 case class CacheConfig(
   cacheType: String = "icache" // icache, dcache
-) {
+) extends Sv39Const {
 // ==========================================================
 // |        tag         |  index |         offset           |
 // |                    |        | bank index | bank offset |
 // ==========================================================
-  val config = CpuConfig()
   val nway   = 2 // 路数，目前只支持2路
-  val nbank  = if (cacheType == "icache") (16 / config.instFetchNum) else 8 // 每个项目中的bank数
+  val nbank  = if (cacheType == "icache") (16 / cpuConfig.instFetchNum) else 8 // 每个项目中的bank数
   val nindex = if (cacheType == "icache") 64 else 64 // 每路的项目数
   val bitsPerBank = // 每个bank的位数
-    if (cacheType == "icache") INST_WID * config.instFetchNum
+    if (cacheType == "icache") INST_WID * cpuConfig.instFetchNum
     else XLEN
   val bytesPerBank    = bitsPerBank / 8 //每个bank中的字节数
   val indexWidth      = log2Ceil(nindex) // index的位宽
   val bankIndexWidth  = log2Ceil(nbank) // bank index的位宽
   val bankOffsetWidth = log2Ceil(bytesPerBank) // bank offset的位宽
   val offsetWidth     = bankIndexWidth + bankOffsetWidth // offset的位宽
-  val tagWidth        = 32 - indexWidth - offsetWidth // tag的位宽
+  val tagWidth        = PADDR_WID - offsetLen // tag的位宽
+  require(offsetWidth + indexWidth == offsetLen) // offsetLen是页内偏移的位宽，为简化设计，这里直接保证每路容量等于页大小
   require(isPow2(nindex))
   require(isPow2(nway))
   require(isPow2(nbank))
   require(isPow2(bytesPerBank))
-  require(
-    tagWidth + indexWidth + offsetWidth == PADDR_WID,
-    "basic request calculation"
-  )
-  require(isPow2(config.instFetchNum))
-  require(config.instFetchNum <= 4, "instFetchNum should be less than 4")
+  require(isPow2(cpuConfig.instFetchNum))
+  require(cpuConfig.instFetchNum <= 4, "instFetchNum should be less than 4")
   require(nbank * nindex * bytesPerBank <= 4 * 1024, "VIPT requires the cache size to be less than 4KB")
 }
diff --git a/chisel/playground/src/Elaborate.scala b/chisel/playground/src/Elaborate.scala
index f37c1fc..c102eb2 100644
--- a/chisel/playground/src/Elaborate.scala
+++ b/chisel/playground/src/Elaborate.scala
@@ -2,10 +2,10 @@ import cpu._
 import circt.stage._
 
 object Elaborate extends App {
-  implicit val config = new CpuConfig()
-  def top             = new PuaCpu()
-  val useMFC          = false // use MLIR-based firrtl compiler
-  val generator       = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
+  implicit val cpuConfig = new CpuConfig()
+  def top                = new PuaCpu()
+  val useMFC             = false // use MLIR-based firrtl compiler
+  val generator          = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
   if (useMFC) {
     (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
   } else {
diff --git a/chisel/playground/src/PuaCpu.scala b/chisel/playground/src/PuaCpu.scala
index 7362d0e..8ae3394 100644
--- a/chisel/playground/src/PuaCpu.scala
+++ b/chisel/playground/src/PuaCpu.scala
@@ -5,7 +5,7 @@ import cpu._
 import cpu.defines._
 
 class PuaCpu extends Module {
-  implicit val config = new CpuConfig()
+  implicit val cpuConfig = new CpuConfig()
   val io = IO(new Bundle {
     val ext_int = Input(new ExtInterrupt())
     val axi     = new AXI()
diff --git a/chisel/playground/src/cache/Cache.scala b/chisel/playground/src/cache/Cache.scala
index 1131f96..e0df71a 100644
--- a/chisel/playground/src/cache/Cache.scala
+++ b/chisel/playground/src/cache/Cache.scala
@@ -7,7 +7,7 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 import cpu.CacheConfig
 
-class Cache(implicit config: CpuConfig) extends Module {
+class Cache(implicit cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val inst = Flipped(new Cache_ICache())
     val data = Flipped(new Cache_DCache())
diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index 9a8759f..9913fb1 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -50,11 +50,11 @@ class WriteBufferUnit extends Bundle {
   val size = UInt(AXI_SIZE_WID.W)
 }
 
-class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module {
+class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Module {
   val nway            = cacheConfig.nway
   val nindex          = cacheConfig.nindex
   val nbank           = cacheConfig.nbank
-  val instFetchNum    = config.instFetchNum
+  val instFetchNum    = cpuConfig.instFetchNum
   val bankOffsetWidth = cacheConfig.bankOffsetWidth
   val bankIndexWidth  = cacheConfig.offsetWidth - bankOffsetWidth
   val bytesPerBank    = cacheConfig.bytesPerBank
diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index b807165..71d1734 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -45,11 +45,11 @@ import cpu.defines.Const._
   =====================================
  */
 
-class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module {
+class ICache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Module {
   val nway            = cacheConfig.nway
   val nindex          = cacheConfig.nindex
   val nbank           = cacheConfig.nbank
-  val instFetchNum    = config.instFetchNum
+  val instFetchNum    = cpuConfig.instFetchNum
   val bankOffsetWidth = cacheConfig.bankOffsetWidth
   val bankIndexWidth  = cacheConfig.offsetWidth - bankOffsetWidth
   val bytesPerBank    = cacheConfig.bytesPerBank
diff --git a/chisel/playground/src/cache/memory/LUTRam.scala b/chisel/playground/src/cache/memory/LUTRam.scala
index 1382e17..7a099ce 100644
--- a/chisel/playground/src/cache/memory/LUTRam.scala
+++ b/chisel/playground/src/cache/memory/LUTRam.scala
@@ -12,7 +12,7 @@ import cpu.CpuConfig
   * @param config
   *   implicit configuration to control generate ram for simulation or elaboration
   */
-class LUTRam(depth: Int, width: Int)(implicit val config: CpuConfig) extends Module {
+class LUTRam(depth: Int, width: Int)(implicit val cpuConfig: CpuConfig) extends Module {
   require(isPow2(depth))
   val waddridth = log2Ceil(depth)
   val io = IO(new Bundle {
@@ -25,14 +25,14 @@ class LUTRam(depth: Int, width: Int)(implicit val config: CpuConfig) extends Mod
     val writeOutput = Output(UInt(width.W))
   })
 
-  if (config.build) {
+  if (cpuConfig.build) {
     val bank = Module(
       new LUTRamIP(
-        wdataidth = width,
-        waddridth = waddridth,
+        wdataidth      = width,
+        waddridth      = waddridth,
         byteWriteWidth = width,
-        numberOfLines = depth,
-      ),
+        numberOfLines  = depth
+      )
     )
     bank.io.clka := clock
     bank.io.clkb := clock
diff --git a/chisel/playground/src/cache/memory/SimpleDualPortRam.scala b/chisel/playground/src/cache/memory/SimpleDualPortRam.scala
index 576d6e4..c8767b2 100644
--- a/chisel/playground/src/cache/memory/SimpleDualPortRam.scala
+++ b/chisel/playground/src/cache/memory/SimpleDualPortRam.scala
@@ -22,7 +22,7 @@ class SimpleDualPortRam(
   byteAddressable: Boolean
 )(
   implicit
-  val config: CpuConfig)
+  val cpuConfig: CpuConfig)
     extends Module {
   require(isPow2(depth))
   require(
@@ -42,7 +42,7 @@ class SimpleDualPortRam(
     val wdata = Input(UInt(width.W))
   })
 
-  if (config.build) {
+  if (cpuConfig.build) {
     val memory = Module(
       new SimpleDualPortRamIP(
         wdataidth      = width,
diff --git a/chisel/playground/src/ctrl/Ctrl.scala b/chisel/playground/src/ctrl/Ctrl.scala
index d6b7eed..d18afe5 100644
--- a/chisel/playground/src/ctrl/Ctrl.scala
+++ b/chisel/playground/src/ctrl/Ctrl.scala
@@ -6,7 +6,7 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class Ctrl(implicit val config: CpuConfig) extends Module {
+class Ctrl(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val cacheCtrl     = Flipped(new CacheCtrl())
     val fetchUnit     = Flipped(new FetchUnitCtrl())
diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index 62c7fa4..9bd1971 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -76,8 +76,8 @@ class ExecuteFuCtrl extends Bundle {
   val allow_to_go = Input(Bool())
 }
 
-class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
-  val inst     = Output(Vec(config.commitNum, new MemRead()))
+class ExecuteCtrl(implicit val cpuConfig: CpuConfig) extends Bundle {
+  val inst     = Output(Vec(cpuConfig.commitNum, new MemRead()))
   val fu_stall = Output(Bool())
   val flush    = Output(Bool())
 
@@ -105,17 +105,17 @@ class WriteBackCtrl extends Bundle {
 }
 
 // cpu to icache
-class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
+class Cache_ICache(implicit val cpuConfig: CpuConfig) extends Bundle {
   // read inst request from cpu
   val req                     = Output(Bool())
   val complete_single_request = Output(Bool()) // !cpu_stall
-  val addr                    = Output(Vec(config.instFetchNum, UInt(XLEN.W))) // virtual address and next virtual address
+  val addr                    = Output(Vec(cpuConfig.instFetchNum, UInt(XLEN.W))) // virtual address and next virtual address
   val fence_i                 = Output(Bool())
   val dcache_stall            = Output(Bool()) // dcache_stall
 
   // read inst result
-  val inst         = Input(Vec(config.instFetchNum, UInt(XLEN.W)))
-  val inst_valid   = Input(Vec(config.instFetchNum, Bool()))
+  val inst         = Input(Vec(cpuConfig.instFetchNum, UInt(XLEN.W)))
+  val inst_valid   = Input(Vec(cpuConfig.instFetchNum, Bool()))
   val acc_err      = Input(Bool())
   val icache_stall = Input(Bool()) // icache_stall
 
diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala
index 6cf04a5..1f08032 100644
--- a/chisel/playground/src/defines/Const.scala
+++ b/chisel/playground/src/defines/Const.scala
@@ -5,9 +5,9 @@ import chisel3.util._
 import cpu.CpuConfig
 
 trait CoreParameter {
-  def config    = new CpuConfig
-  val XLEN      = if (config.isRV32) 32 else 64
-  val VADDR_WID = if (config.isRV32) 32 else 39
+  def cpuConfig = new CpuConfig
+  val XLEN      = if (cpuConfig.isRV32) 32 else 64
+  val VADDR_WID = if (cpuConfig.isRV32) 32 else 39
   val PADDR_WID = 32
 }
 
@@ -56,8 +56,8 @@ object Instructions extends HasInstrType with CoreParameter {
   def NOP           = 0x00000013.U
   val DecodeDefault = List(InstrN, FuType.csr, CSROpType.jmp)
   def DecodeTable = RVIInstr.table ++
-    (if (config.hasMExtension) RVMInstr.table else Array.empty) ++
-    (if (config.hasAExtension) RVAInstr.table else Array.empty) ++
+    (if (cpuConfig.hasMExtension) RVMInstr.table else Array.empty) ++
+    (if (cpuConfig.hasAExtension) RVAInstr.table else Array.empty) ++
     Priviledged.table ++
     RVZicsrInstr.table ++
     RVZifenceiInstr.table
diff --git a/chisel/playground/src/defines/TlbBundles.scala b/chisel/playground/src/defines/TlbBundles.scala
index 62b06d4..6073292 100644
--- a/chisel/playground/src/defines/TlbBundles.scala
+++ b/chisel/playground/src/defines/TlbBundles.scala
@@ -5,13 +5,13 @@ import chisel3.util._
 import cpu.defines.Const._
 import cpu.CacheConfig
 
-sealed trait Sv39Const extends CoreParameter {
+trait Sv39Const extends CoreParameter {
   val PAddrBits = PADDR_WID
   val Level     = 3
-  val offLen    = 12
+  val offsetLen = 12
   val ppn0Len   = 9
   val ppn1Len   = 9
-  val ppn2Len   = PAddrBits - offLen - ppn0Len - ppn1Len // 2
+  val ppn2Len   = PAddrBits - offsetLen - ppn0Len - ppn1Len // 2
   val ppnLen    = ppn2Len + ppn1Len + ppn0Len
   val vpn2Len   = 9
   val vpn1Len   = 9
@@ -32,20 +32,20 @@ sealed trait Sv39Const extends CoreParameter {
   val pteResLen = XLEN - ppnLen - 2 - flagLen
 
   def vaBundle = new Bundle {
-    val vpn2 = UInt(vpn2Len.W)
-    val vpn1 = UInt(vpn1Len.W)
-    val vpn0 = UInt(vpn0Len.W)
-    val off  = UInt(offLen.W)
+    val vpn2   = UInt(vpn2Len.W)
+    val vpn1   = UInt(vpn1Len.W)
+    val vpn0   = UInt(vpn0Len.W)
+    val offset = UInt(offsetLen.W)
   }
 
   def vaBundle2 = new Bundle {
-    val vpn = UInt(vpnLen.W)
-    val off = UInt(offLen.W)
+    val vpn    = UInt(vpnLen.W)
+    val offset = UInt(offsetLen.W)
   }
 
   def vaBundle3 = new Bundle {
-    val vpn = UInt(vpnLen.W)
-    val off = UInt(offLen.W)
+    val vpn    = UInt(vpnLen.W)
+    val offset = UInt(offsetLen.W)
   }
 
   def vpnBundle = new Bundle {
@@ -55,15 +55,15 @@ sealed trait Sv39Const extends CoreParameter {
   }
 
   def paBundle = new Bundle {
-    val ppn2 = UInt(ppn2Len.W)
-    val ppn1 = UInt(ppn1Len.W)
-    val ppn0 = UInt(ppn0Len.W)
-    val off  = UInt(offLen.W)
+    val ppn2   = UInt(ppn2Len.W)
+    val ppn1   = UInt(ppn1Len.W)
+    val ppn0   = UInt(ppn0Len.W)
+    val offset = UInt(offsetLen.W)
   }
 
   def paBundle2 = new Bundle {
-    val ppn = UInt(ppnLen.W)
-    val off = UInt(offLen.W)
+    val ppn    = UInt(ppnLen.W)
+    val offset = UInt(offsetLen.W)
   }
 
   def paddrApply(ppn: UInt, vpnn: UInt): UInt = {
@@ -105,7 +105,7 @@ sealed trait Sv39Const extends CoreParameter {
   }
 
   def maskPaddr(ppn: UInt, vaddr: UInt, mask: UInt) = {
-    MaskData(vaddr, Cat(ppn, 0.U(offLen.W)), Cat(Fill(ppn2Len, 1.U(1.W)), mask, 0.U(offLen.W)))
+    MaskData(vaddr, Cat(ppn, 0.U(offsetLen.W)), Cat(Fill(ppn2Len, 1.U(1.W)), mask, 0.U(offsetLen.W)))
   }
 
   def MaskEQ(mask: UInt, pattern: UInt, vpn: UInt) = {
@@ -122,8 +122,8 @@ class Tlb_ICache extends Bundle {
 
   val translation_ok = Output(Bool())
   val hit            = Output(Bool())
-  val ptag            = Output(UInt(cacheConfig.tagWidth.W))
-  val paddr             = Output(UInt(PADDR_WID.W))
+  val ptag           = Output(UInt(cacheConfig.tagWidth.W))
+  val paddr          = Output(UInt(PADDR_WID.W))
 }
 
 class Tlb_DCache extends Bundle {
@@ -135,6 +135,6 @@ class Tlb_DCache extends Bundle {
 
   val translation_ok = Output(Bool())
   val hit            = Output(Bool())
-  val ptag            = Output(UInt(cacheConfig.tagWidth.W))
-  val paddr             = Output(UInt(PADDR_WID.W))
+  val ptag           = Output(UInt(cacheConfig.tagWidth.W))
+  val paddr          = Output(UInt(PADDR_WID.W))
 }
diff --git a/chisel/playground/src/defines/isa/Priviledged.scala b/chisel/playground/src/defines/isa/Priviledged.scala
index 82766e5..589c8a0 100644
--- a/chisel/playground/src/defines/isa/Priviledged.scala
+++ b/chisel/playground/src/defines/isa/Priviledged.scala
@@ -24,5 +24,5 @@ object Priviledged extends HasInstrType with CoreParameter {
     FENCE  -> List(InstrS, FuType.mou, MOUOpType.fence), // nop    InstrS -> !wen
     WFI    -> List(InstrI, FuType.alu, ALUOpType.add) // nop
     // FENCE          -> List(InstrB, FuType.mou, MOUOpType.fencei)
-  ) ++ (if (config.hasSMode) table_s else Array.empty)
+  ) ++ (if (cpuConfig.hasSMode) table_s else Array.empty)
 }
diff --git a/chisel/playground/src/pipeline/decoder/ARegfile.scala b/chisel/playground/src/pipeline/decoder/ARegfile.scala
index feaaac5..fb7b950 100644
--- a/chisel/playground/src/pipeline/decoder/ARegfile.scala
+++ b/chisel/playground/src/pipeline/decoder/ARegfile.scala
@@ -22,30 +22,30 @@ class RegWrite extends Bundle {
   val wdata = Output(UInt(XLEN.W))
 }
 
-class ARegFile(implicit val config: CpuConfig) extends Module {
+class ARegFile(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
-    val read  = Flipped(Vec(config.decoderNum, new Src12Read()))
-    val write = Flipped(Vec(config.commitNum, new RegWrite()))
+    val read  = Flipped(Vec(cpuConfig.decoderNum, new Src12Read()))
+    val write = Flipped(Vec(cpuConfig.commitNum, new RegWrite()))
   })
 
   // 定义32个32位寄存器
   val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W))))
 
   // 写寄存器堆
-  for (i <- 0 until (config.commitNum)) {
+  for (i <- 0 until (cpuConfig.commitNum)) {
     when(io.write(i).wen && io.write(i).waddr =/= 0.U) {
       regs(io.write(i).waddr) := io.write(i).wdata
     }
   }
 
   // 读寄存器堆
-  for (i <- 0 until (config.decoderNum)) {
+  for (i <- 0 until (cpuConfig.decoderNum)) {
     // src1
     when(io.read(i).src1.raddr === 0.U) {
       io.read(i).src1.rdata := 0.U
     }.otherwise {
       io.read(i).src1.rdata := regs(io.read(i).src1.raddr)
-      for (j <- 0 until (config.commitNum)) {
+      for (j <- 0 until (cpuConfig.commitNum)) {
         when(io.write(j).wen && io.read(i).src1.raddr === io.write(j).waddr) {
           io.read(i).src1.rdata := io.write(j).wdata
         }
@@ -56,7 +56,7 @@ class ARegFile(implicit val config: CpuConfig) extends Module {
       io.read(i).src2.rdata := 0.U
     }.otherwise {
       io.read(i).src2.rdata := regs(io.read(i).src2.raddr)
-      for (j <- 0 until (config.commitNum)) {
+      for (j <- 0 until (cpuConfig.commitNum)) {
         when(io.write(j).wen && io.read(i).src2.raddr === io.write(j).waddr) {
           io.read(i).src2.rdata := io.write(j).wdata
         }
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index 6a9eee6..437789b 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -10,9 +10,9 @@ import cpu.pipeline.execute.DecoderUnitExecuteUnit
 import cpu.pipeline.fetch.BufferUnit
 import cpu.pipeline.execute
 
-class InstFifoDecoderUnit(implicit val config: CpuConfig) extends Bundle {
-  val allow_to_go = Output(Vec(config.decoderNum, Bool()))
-  val inst        = Input(Vec(config.decoderNum, new BufferUnit()))
+class InstFifoDecoderUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
+  val allow_to_go = Output(Vec(cpuConfig.decoderNum, Bool()))
+  val inst        = Input(Vec(cpuConfig.decoderNum, new BufferUnit()))
   val info = Input(new Bundle {
     val empty        = Bool()
     val almost_empty = Bool()
@@ -37,12 +37,12 @@ class DecoderBranchPredictorUnit extends Bundle {
   val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
 }
 
-class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
+class DecoderUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
   val io = IO(new Bundle {
     // 输入
     val instFifo = new InstFifoDecoderUnit()
-    val regfile  = Vec(config.decoderNum, new Src12Read())
-    val forward  = Input(Vec(config.commitNum, new DataForwardToDecoderUnit()))
+    val regfile  = Vec(cpuConfig.decoderNum, new Src12Read())
+    val forward  = Input(Vec(cpuConfig.commitNum, new DataForwardToDecoderUnit()))
     val csr      = Input(new execute.CsrDecoderUnit())
     // 输出
     val fetchUnit = new Bundle {
@@ -54,14 +54,14 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     val ctrl         = new DecoderUnitCtrl()
   })
 
-  val decoder     = Seq.fill(config.decoderNum)(Module(new Decoder()))
+  val decoder     = Seq.fill(cpuConfig.decoderNum)(Module(new Decoder()))
   val jumpCtrl    = Module(new JumpCtrl()).io
   val forwardCtrl = Module(new ForwardCtrl()).io
   val issue       = Module(new Issue()).io
 
   val pc   = io.instFifo.inst.map(_.pc)
   val inst = io.instFifo.inst.map(_.inst)
-  val info = Wire(Vec(config.decoderNum, new InstInfo()))
+  val info = Wire(Vec(cpuConfig.decoderNum, new InstInfo()))
   val mode = io.csr.mode
 
   info          := decoder.map(_.io.out.info)
@@ -71,7 +71,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   issue.allow_to_go          := io.ctrl.allow_to_go
   issue.instFifo             := io.instFifo.info
   io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
-  for (i <- 0 until (config.decoderNum)) {
+  for (i <- 0 until (cpuConfig.decoderNum)) {
     decoder(i).io.in.inst      := inst(i)
     issue.decodeInst(i)        := info(i)
     issue.execute(i).mem_wreg  := io.forward(i).mem_wreg
diff --git a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
index 239e1e3..6bacdbd 100644
--- a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
@@ -7,19 +7,19 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class ForwardCtrl(implicit val config: CpuConfig) extends Module {
+class ForwardCtrl(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
-      val forward = Vec(config.commitNum, new DataForwardToDecoderUnit())
-      val regfile = Vec(config.decoderNum, new Src12Read())
+      val forward = Vec(cpuConfig.commitNum, new DataForwardToDecoderUnit())
+      val regfile = Vec(cpuConfig.decoderNum, new Src12Read())
     })
     val out = Output(new Bundle {
-      val inst = Vec(config.decoderNum, new Src12Read())
+      val inst = Vec(cpuConfig.decoderNum, new Src12Read())
     })
   })
 
   // wb优先度最低
-  for (i <- 0 until (config.decoderNum)) {
+  for (i <- 0 until (cpuConfig.decoderNum)) {
     io.out.inst(i).src1.raddr := DontCare
     io.out.inst(i).src2.raddr := DontCare
     io.out.inst(i).src1.rdata := io.in.regfile(i).src1.rdata
@@ -27,8 +27,8 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
   }
 
   // mem优先度中
-  for (i <- 0 until (config.decoderNum)) {
-    for (j <- 0 until (config.commitNum)) {
+  for (i <- 0 until (cpuConfig.decoderNum)) {
+    for (j <- 0 until (cpuConfig.commitNum)) {
       when(
         io.in.forward(j).mem.wen &&
           io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr
@@ -45,8 +45,8 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
   }
 
   // exe优先度高
-  for (i <- 0 until (config.decoderNum)) {
-    for (j <- 0 until (config.commitNum)) {
+  for (i <- 0 until (cpuConfig.decoderNum)) {
+    for (j <- 0 until (cpuConfig.commitNum)) {
       when(
         io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
           io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr
@@ -63,7 +63,7 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
   }
 
   // 读零寄存器时，数据为0
-  (0 until (config.decoderNum)).foreach(i => {
+  (0 until (cpuConfig.decoderNum)).foreach(i => {
     when(io.in.regfile(i).src1.raddr === 0.U) {
       io.out.inst(i).src1.rdata := 0.U
     }
diff --git a/chisel/playground/src/pipeline/decoder/Issue.scala b/chisel/playground/src/pipeline/decoder/Issue.scala
index 0c02f22..2324e52 100644
--- a/chisel/playground/src/pipeline/decoder/Issue.scala
+++ b/chisel/playground/src/pipeline/decoder/Issue.scala
@@ -7,7 +7,7 @@ import cpu.defines.Const._
 import cpu.defines.Instructions._
 import cpu.CpuConfig
 
-class Issue(implicit val config: CpuConfig) extends Module with HasCSRConst {
+class Issue(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
   val io = IO(new Bundle {
     // 输入
     val allow_to_go = Input(Bool())
@@ -15,15 +15,15 @@ class Issue(implicit val config: CpuConfig) extends Module with HasCSRConst {
       val empty        = Bool()
       val almost_empty = Bool()
     })
-    val decodeInst = Input(Vec(config.decoderNum, new InstInfo()))
-    val execute    = Input(Vec(config.commitNum, new MemRead()))
+    val decodeInst = Input(Vec(cpuConfig.decoderNum, new InstInfo()))
+    val execute    = Input(Vec(cpuConfig.commitNum, new MemRead()))
     // 输出
     val inst1 = Output(new Bundle {
       val allow_to_go = Bool()
     })
   })
 
-  if (config.decoderNum == 2) {
+  if (cpuConfig.decoderNum == 2) {
     val inst0 = io.decodeInst(0)
     val inst1 = io.decodeInst(1)
 
diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
index 0bed0e1..ca99b52 100644
--- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
@@ -7,13 +7,13 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class JumpCtrl(implicit val config: CpuConfig) extends Module {
+class JumpCtrl(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
       val pc       = UInt(XLEN.W)
       val info     = new InstInfo()
       val src_info = new SrcInfo()
-      val forward  = Vec(config.commitNum, new DataForwardToDecoderUnit())
+      val forward  = Vec(cpuConfig.commitNum, new DataForwardToDecoderUnit())
     })
     val out = Output(new Bundle {
       val jump_register = Bool()
@@ -28,7 +28,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
   val jump_inst          = VecInit(BRUOpType.jal).contains(op) && fusel === FuType.bru
   val jump_register_inst = VecInit(BRUOpType.jalr).contains(op) && fusel === FuType.bru
   io.out.jump := (jump_inst || jump_register_inst && !io.out.jump_register) && valid
-  if (config.decoderNum == 2) {
+  if (cpuConfig.decoderNum == 2) {
     io.out.jump_register := jump_register_inst && io.in.info.src1_raddr.orR &&
     ((io.in.forward(0).exe.wen && io.in.info.src1_raddr === io.in.forward(0).exe.waddr) ||
     (io.in.forward(1).exe.wen && io.in.info.src1_raddr === io.in.forward(1).exe.waddr) ||
diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
index e5e14ab..bd826c2 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
@@ -7,7 +7,7 @@ import cpu.defines.Const._
 import cpu.{BranchPredictorConfig, CpuConfig}
 
 class IdExeInst0 extends Bundle {
-  val config   = new BranchPredictorConfig()
+  val cpuConfig   = new BranchPredictorConfig()
   val pc       = UInt(XLEN.W)
   val info     = new InstInfo()
   val src_info = new SrcInfo()
@@ -19,7 +19,7 @@ class IdExeInst0 extends Bundle {
     val branch_inst      = Bool()
     val pred_branch      = Bool()
     val branch_target    = UInt(XLEN.W)
-    val update_pht_index = UInt(config.phtDepth.W)
+    val update_pht_index = UInt(cpuConfig.phtDepth.W)
   }
 }
 
@@ -35,11 +35,11 @@ class DecoderUnitExecuteUnit extends Bundle {
   val inst1 = new IdExeInst1()
 }
 
-class ExecuteStage(implicit val config: CpuConfig) extends Module {
+class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl = Input(new Bundle {
-      val allow_to_go = Vec(config.decoderNum,Bool())
-      val clear             = Vec(config.decoderNum, Bool())
+      val allow_to_go = Vec(cpuConfig.decoderNum,Bool())
+      val clear             = Vec(cpuConfig.decoderNum, Bool())
     })
     val decoderUnit = Input(new DecoderUnitExecuteUnit())
     val executeUnit = Output(new DecoderUnitExecuteUnit())
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index 129293c..db5db7a 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -9,7 +9,7 @@ import cpu.pipeline.decoder.RegWrite
 import cpu.pipeline.memory.ExecuteUnitMemoryUnit
 import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
 
-class ExecuteUnit(implicit val config: CpuConfig) extends Module {
+class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl         = new ExecuteCtrl()
     val executeStage = Input(new DecoderUnitExecuteUnit())
@@ -22,7 +22,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     val decoderUnit = new Bundle {
       val forward = Output(
         Vec(
-          config.commitNum,
+          cpuConfig.commitNum,
           new Bundle {
             val exe          = new RegWrite()
             val exe_mem_wreg = Bool()
diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index 7b13661..7e212e1 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -6,11 +6,11 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class Fu(implicit val config: CpuConfig) extends Module {
+class Fu(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl = new ExecuteFuCtrl()
     val inst = Vec(
-      config.decoderNum,
+      cpuConfig.decoderNum,
       new Bundle {
         val pc       = Input(UInt(XLEN.W))
         val info     = Input(new InstInfo())
@@ -35,7 +35,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
     }
   })
 
-  val alu        = Seq.fill(config.decoderNum)(Module(new Alu()))
+  val alu        = Seq.fill(cpuConfig.decoderNum)(Module(new Alu()))
   val branchCtrl = Module(new BranchCtrl()).io
   val mdu        = Module(new Mdu()).io
 
@@ -51,7 +51,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
   io.branch.flush  := branchCtrl_flush
   io.branch.target := branchCtrl.out.target
 
-  for (i <- 0 until (config.commitNum)) {
+  for (i <- 0 until (cpuConfig.commitNum)) {
     alu(i).io.info     := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new InstInfo()))
     alu(i).io.src_info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).src_info, 0.U.asTypeOf(new SrcInfo()))
   }
@@ -79,7 +79,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
   io.inst(1).result.alu := alu(1).io.result
   io.inst(1).result.mdu := mdu.result
 
-  val mem_addr = Seq.tabulate(config.commitNum)(i =>
+  val mem_addr = Seq.tabulate(cpuConfig.commitNum)(i =>
     Mux(
       LSUOpType.isAMO(io.inst(i).info.op),
       io.inst(i).src_info.src1_data,
diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala
index a38eed1..a63855c 100644
--- a/chisel/playground/src/pipeline/execute/fu/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala
@@ -7,7 +7,7 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 import chisel3.util.experimental.BoringUtils
 
-class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
+class CsrMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
     val pc   = UInt(XLEN.W)
     val ex   = new ExceptionInfo()
@@ -26,7 +26,7 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
   })
 }
 
-class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
+class CsrExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
     val valid    = Bool()
     val pc       = UInt(XLEN.W)
@@ -47,7 +47,7 @@ class CsrDecoderUnit extends Bundle {
   val interrupt = Output(UInt(INT_WID.W))
 }
 
-class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
+class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
   val io = IO(new Bundle {
     val ext_int     = Input(new ExtInterrupt())
     val decoderUnit = new CsrDecoderUnit()
@@ -76,10 +76,10 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   misa_init.mxl := 2.U
   def getMisaExt(ext: Char): UInt = { 1.U << (ext.toInt - 'a'.toInt) }
   var extensions = List('i')
-  if (config.hasMExtension) { extensions = extensions :+ 'm' }
-  if (config.hasAExtension) { extensions = extensions :+ 'a' }
-  if (config.hasSMode) { extensions = extensions :+ 's' }
-  if (config.hasUMode) { extensions = extensions :+ 'u' }
+  if (cpuConfig.hasMExtension) { extensions = extensions :+ 'm' }
+  if (cpuConfig.hasAExtension) { extensions = extensions :+ 'a' }
+  if (cpuConfig.hasSMode) { extensions = extensions :+ 's' }
+  if (cpuConfig.hasUMode) { extensions = extensions :+ 'u' }
   misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i))
   val misa       = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器
   val medeleg    = RegInit(UInt(XLEN.W), 0.U) // 异常代理寄存器
diff --git a/chisel/playground/src/pipeline/execute/fu/Div.scala b/chisel/playground/src/pipeline/execute/fu/Div.scala
index 05db316..777074c 100644
--- a/chisel/playground/src/pipeline/execute/fu/Div.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Div.scala
@@ -40,7 +40,7 @@ class UnsignedDiv extends BlackBox with HasBlackBoxResource {
   })
 }
 
-class Div(implicit config: CpuConfig) extends Module {
+class Div(implicit cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val src1        = Input(UInt(XLEN.W))
     val src2        = Input(UInt(XLEN.W))
@@ -52,7 +52,7 @@ class Div(implicit config: CpuConfig) extends Module {
     val result = Output(UInt((2 * XLEN).W))
   })
 
-  if (config.build) {
+  if (cpuConfig.build) {
     // TODO：未经测试
     val signedDiv   = Module(new SignedDiv()).io
     val unsignedDiv = Module(new UnsignedDiv()).io
@@ -124,7 +124,7 @@ class Div(implicit config: CpuConfig) extends Module {
       Cat(unsignedDiv.m_axis_dout_tdata(XLEN - 1, 0), unsignedDiv.m_axis_dout_tdata((2 * XLEN) - 1, XLEN))
     io.result := Mux(io.signed, signedRes, unsignedRes)
   } else {
-    val cnt = RegInit(0.U(log2Ceil(config.divClockNum + 1).W))
+    val cnt = RegInit(0.U(log2Ceil(cpuConfig.divClockNum + 1).W))
     cnt := MuxCase(
       cnt,
       Seq(
@@ -159,7 +159,7 @@ class Div(implicit config: CpuConfig) extends Module {
       }
     }
 
-    io.ready  := cnt >= config.divClockNum.U
+    io.ready  := cnt >= cpuConfig.divClockNum.U
     io.result := Cat(remainder, quotient)
   }
 }
diff --git a/chisel/playground/src/pipeline/execute/fu/Mdu.scala b/chisel/playground/src/pipeline/execute/fu/Mdu.scala
index eeea066..b62105c 100644
--- a/chisel/playground/src/pipeline/execute/fu/Mdu.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Mdu.scala
@@ -6,7 +6,7 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class Mdu(implicit config: CpuConfig) extends Module {
+class Mdu(implicit cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val info        = Input(new InstInfo())
     val src_info    = Input(new SrcInfo())
diff --git a/chisel/playground/src/pipeline/execute/fu/Mul.scala b/chisel/playground/src/pipeline/execute/fu/Mul.scala
index db5c1d5..50f06c6 100644
--- a/chisel/playground/src/pipeline/execute/fu/Mul.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Mul.scala
@@ -17,7 +17,7 @@ class SignedMul extends BlackBox with HasBlackBoxResource {
   })
 }
 
-class Mul(implicit val config: CpuConfig) extends Module {
+class Mul(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val src1        = Input(UInt((XLEN + 1).W))
     val src2        = Input(UInt((XLEN + 1).W))
@@ -28,10 +28,10 @@ class Mul(implicit val config: CpuConfig) extends Module {
     val result = Output(UInt((2 * XLEN).W))
   })
 
-  if (config.build) {
+  if (cpuConfig.build) {
     // TODO:未经测试
     val signedMul = Module(new SignedMul()).io
-    val cnt       = RegInit(0.U(log2Ceil(config.mulClockNum + 1).W))
+    val cnt       = RegInit(0.U(log2Ceil(cpuConfig.mulClockNum + 1).W))
 
     cnt := MuxCase(
       cnt,
@@ -46,10 +46,10 @@ class Mul(implicit val config: CpuConfig) extends Module {
 
     signedMul.A := io.src1
     signedMul.B := io.src2
-    io.ready    := cnt >= config.mulClockNum.U
+    io.ready    := cnt >= cpuConfig.mulClockNum.U
     io.result   := signedMul.P((2 * XLEN) - 1, 0)
   } else {
-    val cnt = RegInit(0.U(log2Ceil(config.mulClockNum + 1).W))
+    val cnt = RegInit(0.U(log2Ceil(cpuConfig.mulClockNum + 1).W))
     cnt := MuxCase(
       cnt,
       Seq(
@@ -63,6 +63,6 @@ class Mul(implicit val config: CpuConfig) extends Module {
       signed := (io.src1.asSInt * io.src2.asSInt).asUInt
     }
     io.result := signed
-    io.ready  := cnt >= config.mulClockNum.U
+    io.ready  := cnt >= cpuConfig.mulClockNum.U
   }
 }
diff --git a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala
index 1e8f07f..f066d25 100644
--- a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala
+++ b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala
@@ -19,27 +19,27 @@ class ExecuteUnitBranchPredictor extends Bundle {
   val branch           = Output(Bool())
 }
 
-class BranchPredictorIO(implicit config: CpuConfig) extends Bundle {
+class BranchPredictorIO(implicit cpuConfig: CpuConfig) extends Bundle {
   val bpuConfig = new BranchPredictorConfig()
   val decoder   = Flipped(new DecoderBranchPredictorUnit())
 
   val instBuffer = new Bundle {
-    val pc        = Input(Vec(config.instFetchNum, UInt(XLEN.W)))
-    val pht_index = Output(Vec(config.instFetchNum, UInt(bpuConfig.phtDepth.W)))
+    val pc        = Input(Vec(cpuConfig.instFetchNum, UInt(XLEN.W)))
+    val pht_index = Output(Vec(cpuConfig.instFetchNum, UInt(bpuConfig.phtDepth.W)))
   }
 
   val execute = Flipped(new ExecuteUnitBranchPredictor())
 }
 
-class BranchPredictorUnit(implicit config: CpuConfig) extends Module {
+class BranchPredictorUnit(implicit cpuConfig: CpuConfig) extends Module {
   val io = IO(new BranchPredictorIO())
 
-  if (config.branchPredictor == "adaptive") {
+  if (cpuConfig.branchPredictor == "adaptive") {
     val adaptive_predictor = Module(new AdaptiveTwoLevelPredictor())
     io <> adaptive_predictor.io
   }
 
-  if (config.branchPredictor == "global") {
+  if (cpuConfig.branchPredictor == "global") {
     val global_predictor = Module(new GlobalBranchPredictor())
     io <> global_predictor.io
   }
@@ -52,7 +52,7 @@ class GlobalBranchPredictor(
   BHT_DEPTH:   Int = 4 // 取得PC的宽度
 )(
   implicit
-  config: CpuConfig)
+  cpuConfig: CpuConfig)
     extends Module {
   val io = IO(new BranchPredictorIO())
 
@@ -98,7 +98,7 @@ class GlobalBranchPredictor(
 class AdaptiveTwoLevelPredictor(
 )(
   implicit
-  config: CpuConfig)
+  cpuConfig: CpuConfig)
     extends Module {
   val bpuConfig = new BranchPredictorConfig()
   val PHT_DEPTH = bpuConfig.phtDepth
@@ -117,7 +117,7 @@ class AdaptiveTwoLevelPredictor(
   val pht       = RegInit(VecInit(Seq.fill(1 << PHT_DEPTH)(strongly_taken)))
   val pht_index = io.decoder.pht_index
 
-  for (i <- 0 until config.instFetchNum) {
+  for (i <- 0 until cpuConfig.instFetchNum) {
     io.instBuffer.pht_index(i) := bht(io.instBuffer.pc(i)(1 + BHT_DEPTH, 2))
   }
 
diff --git a/chisel/playground/src/pipeline/fetch/FetchUnit.scala b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
index b712672..415634d 100644
--- a/chisel/playground/src/pipeline/fetch/FetchUnit.scala
+++ b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
@@ -7,7 +7,7 @@ import cpu.CpuConfig
 
 class FetchUnit(
   implicit
-  val config: CpuConfig)
+  val cpuConfig: CpuConfig)
     extends Module {
   val io = IO(new Bundle {
     val memory = new Bundle {
@@ -26,7 +26,7 @@ class FetchUnit(
       val full = Input(Bool())
     }
     val iCache = new Bundle {
-      val inst_valid = Input(Vec(config.instFetchNum, Bool()))
+      val inst_valid = Input(Vec(cpuConfig.instFetchNum, Bool()))
       val pc         = Output(UInt(XLEN.W))
       val pc_next    = Output(UInt(XLEN.W))
     }
@@ -40,7 +40,7 @@ class FetchUnit(
   val pc_next_temp = Wire(UInt(XLEN.W))
 
   pc_next_temp := pc
-  for (i <- 0 until config.instFetchNum) {
+  for (i <- 0 until cpuConfig.instFetchNum) {
     when(io.iCache.inst_valid(i)) {
       pc_next_temp := pc + ((i + 1) * 4).U
     }
diff --git a/chisel/playground/src/pipeline/fetch/InstFifo.scala b/chisel/playground/src/pipeline/fetch/InstFifo.scala
index 478372b..e8ffaf7 100644
--- a/chisel/playground/src/pipeline/fetch/InstFifo.scala
+++ b/chisel/playground/src/pipeline/fetch/InstFifo.scala
@@ -13,31 +13,31 @@ class BufferUnit extends Bundle {
   val pc        = UInt(XLEN.W)
 }
 
-class InstFifo(implicit val config: CpuConfig) extends Module {
+class InstFifo(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val do_flush = Input(Bool())
 
-    val ren  = Input(Vec(config.decoderNum, Bool()))
-    val read = Output(Vec(config.decoderNum, new BufferUnit()))
+    val ren  = Input(Vec(cpuConfig.decoderNum, Bool()))
+    val read = Output(Vec(cpuConfig.decoderNum, new BufferUnit()))
 
-    val wen   = Input(Vec(config.instFetchNum, Bool()))
-    val write = Input(Vec(config.instFetchNum, new BufferUnit()))
+    val wen   = Input(Vec(cpuConfig.instFetchNum, Bool()))
+    val write = Input(Vec(cpuConfig.instFetchNum, new BufferUnit()))
 
     val empty        = Output(Bool())
     val almost_empty = Output(Bool())
     val full         = Output(Bool())
   })
   // fifo buffer
-  val buffer = RegInit(VecInit(Seq.fill(config.instFifoDepth)(0.U.asTypeOf(new BufferUnit()))))
+  val buffer = RegInit(VecInit(Seq.fill(cpuConfig.instFifoDepth)(0.U.asTypeOf(new BufferUnit()))))
 
   // fifo ptr
-  val enq_ptr = RegInit(0.U(log2Ceil(config.instFifoDepth).W))
-  val deq_ptr = RegInit(0.U(log2Ceil(config.instFifoDepth).W))
-  val count   = RegInit(0.U(log2Ceil(config.instFifoDepth).W))
+  val enq_ptr = RegInit(0.U(log2Ceil(cpuConfig.instFifoDepth).W))
+  val deq_ptr = RegInit(0.U(log2Ceil(cpuConfig.instFifoDepth).W))
+  val count   = RegInit(0.U(log2Ceil(cpuConfig.instFifoDepth).W))
 
   // config.instFifoDepth - 1 is the last element, config.instFifoDepth - 2 is the last second element
   // the second last element's valid decide whether the fifo is full
-  io.full         := count >= (config.instFifoDepth - config.instFetchNum).U // TODO:这里的等于号还可以优化
+  io.full         := count >= (cpuConfig.instFifoDepth - cpuConfig.instFetchNum).U // TODO:这里的等于号还可以优化
   io.empty        := count === 0.U
   io.almost_empty := count === 1.U
 
@@ -72,9 +72,9 @@ class InstFifo(implicit val config: CpuConfig) extends Module {
   }
 
   // * enq * //
-  val enq_num = Wire(UInt(log2Ceil(config.instFetchNum + 1).W))
+  val enq_num = Wire(UInt(log2Ceil(cpuConfig.instFetchNum + 1).W))
 
-  for (i <- 0 until config.instFetchNum) {
+  for (i <- 0 until cpuConfig.instFetchNum) {
     when(io.wen(i)) {
       buffer(enq_ptr + i.U) := io.write(i)
     }
@@ -87,11 +87,11 @@ class InstFifo(implicit val config: CpuConfig) extends Module {
   }
 
   enq_num := 0.U
-  for (i <- 0 until config.instFetchNum) {
+  for (i <- 0 until cpuConfig.instFetchNum) {
     when(io.wen(i)) {
       enq_num := (i + 1).U
     }
   }
 
-  count := Mux(io.do_flush, 0.U, count + enq_num + config.instFifoDepth.U - deq_num)
+  count := Mux(io.do_flush, 0.U, count + enq_num + cpuConfig.instFifoDepth.U - deq_num)
 }
diff --git a/chisel/playground/src/pipeline/memory/Lsu.scala b/chisel/playground/src/pipeline/memory/Lsu.scala
index 6a4bcfd..6c9e89b 100644
--- a/chisel/playground/src/pipeline/memory/Lsu.scala
+++ b/chisel/playground/src/pipeline/memory/Lsu.scala
@@ -48,7 +48,7 @@ class Lsu_MemoryUnit extends Bundle {
   })
 }
 
-class Lsu(implicit val config: CpuConfig) extends Module {
+class Lsu(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val memoryUnit = new Lsu_MemoryUnit()
     val dataMemory = new Lsu_DataMemory()
diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala
index d309e9d..1dd083b 100644
--- a/chisel/playground/src/pipeline/memory/MemoryStage.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala
@@ -14,12 +14,12 @@ class ExeMemInst extends Bundle {
   val ex       = new ExceptionInfo()
 }
 
-class ExecuteUnitMemoryUnit(implicit val config: CpuConfig) extends Bundle {
+class ExecuteUnitMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
   val inst0 = new ExeMemInst()
   val inst1 = new ExeMemInst()
 }
 
-class MemoryStage(implicit val config: CpuConfig) extends Module {
+class MemoryStage(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl = Input(new Bundle {
       val allow_to_go = Bool()
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index 64adeac..4fa805e 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -9,7 +9,7 @@ import cpu.pipeline.decoder.RegWrite
 import cpu.pipeline.execute.CsrMemoryUnit
 import cpu.pipeline.writeback.MemoryUnitWriteBackUnit
 
-class MemoryUnit(implicit val config: CpuConfig) extends Module {
+class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl        = new MemoryCtrl()
     val memoryStage = Input(new ExecuteUnitMemoryUnit())
@@ -17,7 +17,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
       val flush  = Bool()
       val target = UInt(XLEN.W)
     })
-    val decoderUnit    = Output(Vec(config.commitNum, new RegWrite()))
+    val decoderUnit    = Output(Vec(cpuConfig.commitNum, new RegWrite()))
     val csr            = Flipped(new CsrMemoryUnit())
     val writeBackStage = Output(new MemoryUnitWriteBackUnit())
     val dataMemory     = new Lsu_DataMemory()
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
index b1677f3..9f13054 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
@@ -17,7 +17,7 @@ class MemoryUnitWriteBackUnit extends Bundle {
   val inst0 = new MemWbInst()
   val inst1 = new MemWbInst()
 }
-class WriteBackStage(implicit val config: CpuConfig) extends Module {
+class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl = Input(new Bundle {
       val allow_to_go = Bool()
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 757ef5a..1f72ec2 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -7,11 +7,11 @@ import cpu.defines.Const._
 import cpu.pipeline.decoder.RegWrite
 import cpu.CpuConfig
 
-class WriteBackUnit(implicit val config: CpuConfig) extends Module {
+class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val ctrl           = new WriteBackCtrl()
     val writeBackStage = Input(new MemoryUnitWriteBackUnit())
-    val regfile        = Output(Vec(config.commitNum, new RegWrite()))
+    val regfile        = Output(Vec(cpuConfig.commitNum, new RegWrite()))
     val debug          = new DEBUG()
   })
 
@@ -32,7 +32,7 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
   io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
   io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
 
-  if (config.hasCommitBuffer) {
+  if (cpuConfig.hasCommitBuffer) {
     val buffer = Module(new CommitBuffer()).io
     buffer.enq(0).wb_pc       := io.writeBackStage.inst0.pc
     buffer.enq(0).wb_rf_wen   := io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go
diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala
index d97b3e5..08a0b47 100644
--- a/chisel/playground/test/src/TestMain.scala
+++ b/chisel/playground/test/src/TestMain.scala
@@ -5,7 +5,7 @@ import cpu.pipeline.execute.Csr
 import cache.DCache
 
 object TestMain extends App {
-  implicit val config       = new CpuConfig()
+  implicit val cpuConfig       = new CpuConfig()
   implicit val dCacheConfig = CacheConfig(cacheType = "dcache")
   def top                   = new DCache(dCacheConfig)
   val useMFC                = false // use MLIR-based firrtl compiler