增加指令集

chisel/playground/src/defines/Const.scala

@@ -15,13 +15,6 @@ trait Constants extends CoreParameter {
   def PC_WID  = XLEN
   def PC_INIT = "h60000000".U(PC_WID.W)
 
-  def EXT_INT_WID = 6
-  def HILO_WID    = 64
-
-  def WRITE_ENABLE  = true.B
-  def WRITE_DISABLE = false.B
-  def READ_ENABLE   = true.B
-  def READ_DISABLE  = false.B
   def SINGLE_ISSUE  = false.B
   def DUAL_ISSUE    = true.B
 
@@ -108,5 +101,7 @@ object Instructions extends HasInstrType with CoreParameter {
   def NOP           = 0x00000013.U
   val DecodeDefault = List(InstrN, FuType.csr, CSROpType.jmp)
   def DecodeTable = RVIInstr.table ++ (if (config.hasMExtension) RVMInstr.table else Array.empty) ++
-    Priviledged.table
+    Priviledged.table ++
+    RVAInstr.table ++
+    RVZicsrInstr.table ++ RVZifenceiInstr.table
 }

chisel/playground/src/defines/Util.scala

@@ -53,4 +53,15 @@ object Util {
     require(to > from && from >= 1)
     Cat(Fill(to - from, 0.U), raw)
   }
+
+  object LookupTree {
+    def apply[T <: Data](key: UInt, mapping: Iterable[(UInt, T)]): T =
+      Mux1H(mapping.map(p => (p._1 === key, p._2)))
+  }
+
+  object LookupTreeDefault {
+    def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
+      MuxLookup(key, default, mapping.toSeq)
+  }
+
 }

chisel/playground/src/defines/isa/Instructions.scala

@@ -17,6 +17,13 @@ trait HasInstrType {
   def isrfWen(instrType: UInt): Bool = instrType(2)
 }
 
+object SrcType {
+  def reg     = "b0".U
+  def pc      = "b1".U
+  def imm     = "b1".U
+  def apply() = UInt(1.W)
+}
+
 object FuType {
   def num     = 5
   def alu     = "b000".U
@@ -28,6 +35,10 @@ object FuType {
   def apply() = UInt(log2Up(num).W)
 }
 
+object FuOpType {
+  def apply() = UInt(7.W)
+}
+
 // BTB
 object BTBtype {
   def B = "b00".U // branch

chisel/playground/src/defines/isa/RVA.scala

@@ -0,0 +1,42 @@
+package cpu.defines
+
+import chisel3._
+import chisel3.util._
+
+object RVAInstr extends HasInstrType {
+  // Note: use instr(14,12) to distinguish D/W inst
+  // def LR      = BitPat("b00010??00000_?????_???_?????_0101111")
+  // def SC      = BitPat("b00011??00000_?????_???_?????_0101111")
+  def LR_D    = BitPat("b00010_??_00000_?????_011_?????_0101111")
+  def SC_D    = BitPat("b00011_??_?????_?????_011_?????_0101111")
+  def LR_W    = BitPat("b00010_??_00000_?????_010_?????_0101111")
+  def SC_W    = BitPat("b00011_??_?????_?????_010_?????_0101111")
+  def AMOSWAP = BitPat("b00001_??_?????_?????_01?_?????_0101111")
+  def AMOADD  = BitPat("b00000_??_?????_?????_01?_?????_0101111")
+  def AMOXOR  = BitPat("b00100_??_?????_?????_01?_?????_0101111")
+  def AMOAND  = BitPat("b01100_??_?????_?????_01?_?????_0101111")
+  def AMOOR   = BitPat("b01000_??_?????_?????_01?_?????_0101111")
+  def AMOMIN  = BitPat("b10000_??_?????_?????_01?_?????_0101111")
+  def AMOMAX  = BitPat("b10100_??_?????_?????_01?_?????_0101111")
+  def AMOMINU = BitPat("b11000_??_?????_?????_01?_?????_0101111")
+  def AMOMAXU = BitPat("b11100_??_?????_?????_01?_?????_0101111")
+  // funct3 === 010 or 011
+
+  val table = Array(
+    // LR          -> List(InstrI, FuType.lsu, LSUOpType.lr),
+    LR_D -> List(InstrI, FuType.lsu, LSUOpType.lr),
+    LR_W -> List(InstrI, FuType.lsu, LSUOpType.lr),
+    // SC          -> List(InstrS, FuType.lsu, LSUOpType.sc),
+    SC_D    -> List(InstrSA, FuType.lsu, LSUOpType.sc),
+    SC_W    -> List(InstrSA, FuType.lsu, LSUOpType.sc),
+    AMOSWAP -> List(InstrR, FuType.lsu, LSUOpType.amoswap),
+    AMOADD  -> List(InstrR, FuType.lsu, LSUOpType.amoadd),
+    AMOXOR  -> List(InstrR, FuType.lsu, LSUOpType.amoxor),
+    AMOAND  -> List(InstrR, FuType.lsu, LSUOpType.amoand),
+    AMOOR   -> List(InstrR, FuType.lsu, LSUOpType.amoor),
+    AMOMIN  -> List(InstrR, FuType.lsu, LSUOpType.amomin),
+    AMOMAX  -> List(InstrR, FuType.lsu, LSUOpType.amomax),
+    AMOMINU -> List(InstrR, FuType.lsu, LSUOpType.amominu),
+    AMOMAXU -> List(InstrR, FuType.lsu, LSUOpType.amomaxu)
+  )
+}

chisel/playground/src/defines/isa/RVZicsr.scala

@@ -0,0 +1,22 @@
+package cpu.defines
+
+import chisel3._
+import chisel3.util._
+
+object RVZicsrInstr extends HasInstrType {
+  def CSRRW  = BitPat("b????????????_?????_001_?????_1110011")
+  def CSRRS  = BitPat("b????????????_?????_010_?????_1110011")
+  def CSRRC  = BitPat("b????????????_?????_011_?????_1110011")
+  def CSRRWI = BitPat("b????????????_?????_101_?????_1110011")
+  def CSRRSI = BitPat("b????????????_?????_110_?????_1110011")
+  def CSRRCI = BitPat("b????????????_?????_111_?????_1110011")
+
+  val table = Array(
+    CSRRW  -> List(InstrI, FuType.csr, CSROpType.wrt),
+    CSRRS  -> List(InstrI, FuType.csr, CSROpType.set),
+    CSRRC  -> List(InstrI, FuType.csr, CSROpType.clr),
+    CSRRWI -> List(InstrI, FuType.csr, CSROpType.wrti),
+    CSRRSI -> List(InstrI, FuType.csr, CSROpType.seti),
+    CSRRCI -> List(InstrI, FuType.csr, CSROpType.clri)
+  )
+}

chisel/playground/src/defines/isa/RVZifencei.scala

@@ -0,0 +1,12 @@
+package cpu.defines
+
+import chisel3._
+import chisel3.util._
+
+object RVZifenceiInstr extends HasInstrType {
+  def FENCEI = BitPat("b000000000000_00000_001_00000_0001111")
+
+  val table = Array(
+    FENCEI -> List(InstrB, FuType.mou, MOUOpType.fencei)
+  )
+}