From 71957704485027f1e12162011f86f93bfb3d81b3 Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 28 Nov 2023 16:46:33 +0800 Subject: [PATCH] =?UTF-8?q?fix(icache):=20acc=20err=E6=97=B6=E5=BA=94?= =?UTF-8?q?=E8=AF=A5=E6=8A=8Avalid=E7=BD=AE=E4=B8=BA1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index aeddb06..239f3c2 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -45,7 +45,7 @@ class ICache(implicit config: CpuConfig) extends Module { io.cpu.acc_err := acc_err (0 until config.instFetchNum).foreach(i => { io.cpu.inst(i) := saved(i).inst - io.cpu.inst_valid(i) := saved(i).valid + io.cpu.inst_valid(i) := saved(i).valid || acc_err }) io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR