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perf(lsu): 修改完成信号的逻辑

This commit is contained in:
Liphen 2023-12-29 12:07:18 +08:00
parent e81d0d2b8c
commit 71543700c8
1 changed files with 3 additions and 2 deletions
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5
chisel/playground/src/pipeline/memory/Lsu.scala
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@ -139,7 +139,8 @@ class Lsu(implicit val config: CpuConfig) extends Module {
lsExe.in.wdata := DontCare lsExe.in.wdata := DontCare
io.memoryUnit.out.ready := false.B io.memoryUnit.out.ready := false.B
when(lsExe.out.ready) { when(lsExe.out.ready) {
state := s_amo_a; state := s_amo_a;
// 告诉dcache已经完成一次访存操作，可以进入下一次访存
complete_single_request := true.B complete_single_request := true.B
} }
atomMemReg := lsExe.out.rdata atomMemReg := lsExe.out.rdata
@ -147,7 +148,6 @@ class Lsu(implicit val config: CpuConfig) extends Module {
} }
is(s_amo_a) { is(s_amo_a) {
complete_single_request := false.B
lsExe.in.mem_en := false.B lsExe.in.mem_en := false.B
lsExe.in.mem_addr := DontCare lsExe.in.mem_addr := DontCare
lsExe.in.info.op := DontCare lsExe.in.info.op := DontCare
@ -187,6 +187,7 @@ class Lsu(implicit val config: CpuConfig) extends Module {
) { ) {
state := s_idle state := s_idle
io.memoryUnit.out.ready := true.B io.memoryUnit.out.ready := true.B
complete_single_request := false.B // 发生例外时应该由ctrl的allow to go控制
} }
setLr := io.memoryUnit.out.ready && (lrReq || scReq) setLr := io.memoryUnit.out.ready && (lrReq || scReq)