From 6fb565b51f8a1e8f1ec8fc69bfd7844093c2cecb Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Sat, 20 Jan 2024 14:18:53 +0800
Subject: [PATCH] =?UTF-8?q?fix(tlb):=20=E4=BF=AE=E5=A4=8Dvma=E6=8C=87?=
 =?UTF-8?q?=E4=BB=A4=E9=94=99=E8=AF=AF?=
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---
 chisel/playground/src/cache/mmu/Tlb.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/chisel/playground/src/cache/mmu/Tlb.scala b/chisel/playground/src/cache/mmu/Tlb.scala
index 308368f..9822f15 100644
--- a/chisel/playground/src/cache/mmu/Tlb.scala
+++ b/chisel/playground/src/cache/mmu/Tlb.scala
@@ -360,7 +360,9 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
     }
   }
 
-  val src1 = io.sfence_vma.src_info.src1_data(vpnLen - 1, 0)
+  // vpn
+  val src1 = io.sfence_vma.src_info.src1_data(vpnLen - 1, pageOffsetLen)
+  // asid
   val src2 = io.sfence_vma.src_info.src2_data(asidLen - 1, 0)
   when(io.sfence_vma.valid) {
     when(!src1.orR && !src2.orR) {