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fix(dcache): 修复wstrb，修复cache大小限制

This commit is contained in:
Liphen 2023-12-28 18:30:02 +08:00
parent 1e11239281
commit 6f5df6895e
2 changed files with 13 additions and 14 deletions
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5
chisel/playground/src/CpuConfig.scala
View File

@ -36,9 +36,8 @@ case class CacheConfig(
// ==========================================================
val config = CpuConfig()
val nway = 2 // 路数，目前只支持2路
// FIXME:增加DCache的大小，当数量增加时如设置8，128时会报栈溢出的错误
val nbank = if (cacheType == "icache") 4 else 4 // 每个项目中的bank数
val nindex = if (cacheType == "icache") 64 else 64 // 每路的项目数
val nbank = if (cacheType == "icache") 4 else 8 // 每个项目中的bank数
val nindex = if (cacheType == "icache") 64 else 128 // 每路的项目数
val bitsPerBank = // 每个bank的位数
if (cacheType == "icache") INST_WID * config.instFetchNum
else XLEN

22
chisel/playground/src/cache/DCache.scala vendored
View File

@ -127,7 +127,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
val use_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait)
val do_replace = RegInit(false.B)
val replace_index = io.cpu.addr(indexWidth + offsetWidth - 1, offsetWidth)
val replace_wstrb = Wire(Vec(nway, Vec(nbank, UInt(AXI_STRB_WID.W))))
val replace_wstrb = Wire(Vec(nbank, Vec(nway, UInt(AXI_STRB_WID.W))))
val replace_wdata = Mux(state === s_replace, io.axi.r.bits.data, io.cpu.wdata)
val replace_way = lru(replace_index)
@ -138,7 +138,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
val tag_wdata = RegInit(0.U(tagWidth.W))
val data = Wire(Vec(nway, Vec(nbank, UInt(XLEN.W))))
val data = Wire(Vec(nbank, Vec(nway, UInt(XLEN.W))))
val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
val tag_compare_valid = Wire(Vec(nway, Bool()))
@ -159,7 +159,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
val saved_rdata = RegInit(0.U(XLEN.W))
io.cpu.rdata := Mux(state === s_wait, saved_rdata, data(select_way)(replace_index))
io.cpu.rdata := Mux(state === s_wait, saved_rdata, data(replace_index)(select_way))
// bank tagv ram
for { i <- 0 until nway } {
@ -167,12 +167,12 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
for { j <- 0 until nbank } {
bank(j).io.ren := true.B
bank(j).io.raddr := Mux(use_next_addr, exe_index, replace_index)
data(i)(j) := bank(j).io.rdata
data(j)(i) := bank(j).io.rdata
bank(j).io.wen := replace_wstrb(i)(j).orR
bank(j).io.wen := replace_wstrb(j)(i).orR
bank(j).io.waddr := replace_index
bank(j).io.wdata := replace_wdata
bank(j).io.wstrb := replace_wstrb(i)(j)
bank(j).io.wstrb := replace_wstrb(j)(i)
val tagRam = Module(new LUTRam(nindex, tagWidth))
tagRam.io.raddr := tag_rindex
@ -184,10 +184,10 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
tag_compare_valid(i) := tag(i) === io.cpu.tlb.ptag && valid(replace_index)(i) && io.cpu.tlb.translation_ok
replace_wstrb(i)(j) := Mux(
replace_wstrb(j)(i) := Mux(
tag_compare_valid(i) && io.cpu.en && io.cpu.wen.orR && !io.cpu.tlb.uncached && state === s_idle && !tlb_fill,
io.cpu.wstrb,
burst.wstrb(i)(j)
Fill(AXI_STRB_WID, burst.wstrb(i)(j))
)
}
}
@ -285,7 +285,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
burst.wstrb(replace_way) := 1.U // 先写入第一块bank
when(replace_dirty) {
// cache行的脏位为真时需要写回，备份一下cache行，便于处理读写时序问题
(0 until nbank).map(i => bank_replication(i) := data(select_way)(i))
(0 until nbank).map(i => bank_replication(i) := data(i)(select_way))
}
}.otherwise {
when(io.cpu.dcache_ready) {
@ -295,7 +295,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
dirty(replace_index)(select_way) := true.B
}
when(!io.cpu.complete_single_request) {
saved_rdata := data(select_way)(bank_index)
saved_rdata := data(bank_index)(select_way)
state := s_wait
}
}
@ -433,7 +433,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
aw.len := cached_len.U
aw.size := cached_size.U
awvalid := true.B
w.data := data(replace_way)(bank_woffset)
w.data := data(bank_woffset)(replace_way)
w.strb := ~0.U(AXI_STRB_WID.W)
w.last := false.B
wvalid := true.B