From 6f065a9c67012fcb83d0608d0b6a7551b7357780 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 13 Dec 2023 19:40:01 +0800 Subject: [PATCH] =?UTF-8?q?perf:=20=E7=BC=A9=E5=87=8Fop=E4=BF=A1=E5=8F=B7?= =?UTF-8?q?=EF=BC=8C=E5=A2=9E=E5=8A=A0bru?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../src/defines/isa/Instructions.scala | 62 ++++++++++--------- chisel/playground/src/defines/isa/RVI.scala | 16 ++--- .../src/pipeline/decoder/Issue.scala | 4 +- .../src/pipeline/decoder/JumpCtrl.scala | 4 +- .../src/pipeline/execute/BranchCtrl.scala | 14 ++--- .../src/pipeline/execute/ExecuteUnit.scala | 11 ++-- .../playground/src/pipeline/execute/Fu.scala | 6 +- .../pipeline/fetch/BranchPredictorUnit.scala | 6 +- 8 files changed, 60 insertions(+), 63 deletions(-) diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala index 620cab6..3b60032 100644 --- a/chisel/playground/src/defines/isa/Instructions.scala +++ b/chisel/playground/src/defines/isa/Instructions.scala @@ -25,13 +25,13 @@ object SrcType { } object FuType { - def num = 5 + def num = 6 def alu = "b000".U // arithmetic logic unit def lsu = "b001".U // load store unit def mdu = "b010".U // mul div unit def csr = "b011".U // control status register def mou = "b100".U // memory order unit - def bru = alu + def bru = "b101".U // branch unit def apply() = UInt(log2Up(num).W) } @@ -51,38 +51,40 @@ object BTBtype { // ALU object ALUOpType { - def add = "b1000000".U - def sll = "b0000001".U - def slt = "b0000010".U - def sltu = "b0000011".U - def xor = "b0000100".U - def srl = "b0000101".U - def or = "b0000110".U - def and = "b0000111".U - def sub = "b0001000".U - def sra = "b0001101".U + def add = "b100000".U + def sll = "b000001".U + def slt = "b000010".U + def sltu = "b000011".U + def xor = "b000100".U + def srl = "b000101".U + def or = "b000110".U + def and = "b000111".U + def sub = "b001000".U + def sra = "b001101".U - def addw = "b1100000".U - def subw = "b0101000".U - def sllw = "b0100001".U - def srlw = "b0100101".U - def sraw = "b0101101".U + def addw = "b110000".U + def subw = "b011000".U + def sllw = "b010001".U + def srlw = "b010101".U + def sraw = "b011101".U - def isWordOp(func: UInt) = func(5) + def isWordOp(func: UInt) = func(4) + def isAdd(func: UInt) = func(5) +} - def jal = "b1011000".U - def jalr = "b1011010".U - def beq = "b0010000".U - def bne = "b0010001".U - def blt = "b0010100".U - def bge = "b0010101".U - def bltu = "b0010110".U - def bgeu = "b0010111".U +object BRUOpType { + def jal = "b1000".U + def jalr = "b1010".U + def beq = "b0000".U + def bne = "b0001".U + def blt = "b0100".U + def bge = "b0101".U + def bltu = "b0110".U + def bgeu = "b0111".U - def isAdd(func: UInt) = func(6) - def isBru(func: UInt) = func(4) - def isBranch(func: UInt) = isBru(func) && !func(3) - def isJump(func: UInt) = isBru(func) && !isBranch(func) + def isBranch(func: UInt) = !func(3) + def isJump(func: UInt) = !isBranch(func) + def isAdd(func: UInt) = isJump(func) def getBranchType(func: UInt) = func(2, 1) def isBranchInvert(func: UInt) = func(0) } diff --git a/chisel/playground/src/defines/isa/RVI.scala b/chisel/playground/src/defines/isa/RVI.scala index ed55ccb..fc0e6a7 100644 --- a/chisel/playground/src/defines/isa/RVI.scala +++ b/chisel/playground/src/defines/isa/RVI.scala @@ -68,14 +68,14 @@ object RV32I_BRUInstr extends HasInstrType { def BGEU = BitPat("b???????_?????_?????_111_?????_1100011") val table = Array( - JAL -> List(InstrJ, FuType.bru, ALUOpType.jal), - JALR -> List(InstrI, FuType.bru, ALUOpType.jalr), - BEQ -> List(InstrB, FuType.bru, ALUOpType.beq), - BNE -> List(InstrB, FuType.bru, ALUOpType.bne), - BLT -> List(InstrB, FuType.bru, ALUOpType.blt), - BGE -> List(InstrB, FuType.bru, ALUOpType.bge), - BLTU -> List(InstrB, FuType.bru, ALUOpType.bltu), - BGEU -> List(InstrB, FuType.bru, ALUOpType.bgeu) + JAL -> List(InstrJ, FuType.bru, BRUOpType.jal), + JALR -> List(InstrI, FuType.bru, BRUOpType.jalr), + BEQ -> List(InstrB, FuType.bru, BRUOpType.beq), + BNE -> List(InstrB, FuType.bru, BRUOpType.bne), + BLT -> List(InstrB, FuType.bru, BRUOpType.blt), + BGE -> List(InstrB, FuType.bru, BRUOpType.bge), + BLTU -> List(InstrB, FuType.bru, BRUOpType.bltu), + BGEU -> List(InstrB, FuType.bru, BRUOpType.bgeu) ) } diff --git a/chisel/playground/src/pipeline/decoder/Issue.scala b/chisel/playground/src/pipeline/decoder/Issue.scala index 036179a..a17f7ca 100644 --- a/chisel/playground/src/pipeline/decoder/Issue.scala +++ b/chisel/playground/src/pipeline/decoder/Issue.scala @@ -53,8 +53,8 @@ class Issue(implicit val config: CpuConfig) extends Module { // 指令0为bru指令 val is_bru = VecInit( - inst0.fusel === FuType.bru && ALUOpType.isBru(io.decodeInst(0).op), - inst1.fusel === FuType.bru && ALUOpType.isBru(io.decodeInst(1).op) + inst0.fusel === FuType.bru, + inst1.fusel === FuType.bru ) // 指令1是否允许执行 diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala index 98c2583..208edcc 100644 --- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala +++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala @@ -26,8 +26,8 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module { val valid = io.in.info.valid val op = io.in.info.op val fusel = io.in.info.fusel - val jump_inst = VecInit(ALUOpType.jal).contains(op) && fusel === FuType.bru - val jump_register_inst = VecInit(ALUOpType.jalr).contains(op) && fusel === FuType.bru + val jump_inst = VecInit(BRUOpType.jal).contains(op) && fusel === FuType.bru + val jump_register_inst = VecInit(BRUOpType.jalr).contains(op) && fusel === FuType.bru io.out.jump_inst := jump_inst || jump_register_inst io.out.jump := (jump_inst || jump_register_inst && !io.out.jump_register) && valid if (config.decoderNum == 2) { diff --git a/chisel/playground/src/pipeline/execute/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/BranchCtrl.scala index 4098dba..c177b62 100644 --- a/chisel/playground/src/pipeline/execute/BranchCtrl.scala +++ b/chisel/playground/src/pipeline/execute/BranchCtrl.scala @@ -22,23 +22,23 @@ class BranchCtrl extends Module { } }) val valid = - io.in.info.fusel === FuType.bru && ALUOpType.isBranch(io.in.info.op) && io.in.info.valid + io.in.info.fusel === FuType.bru && BRUOpType.isBranch(io.in.info.op) && io.in.info.valid val src1 = io.in.src_info.src1_data val src2 = io.in.src_info.src2_data val op = io.in.info.op - val is_sub = !ALUOpType.isAdd(op) + val is_sub = !BRUOpType.isAdd(op) val adder = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub val xor = src1 ^ src2 val sltu = !adder(XLEN) val slt = xor(XLEN - 1) ^ sltu val table = List( - ALUOpType.getBranchType(ALUOpType.beq) -> !xor.orR, - ALUOpType.getBranchType(ALUOpType.blt) -> slt, - ALUOpType.getBranchType(ALUOpType.bltu) -> sltu + BRUOpType.getBranchType(BRUOpType.beq) -> !xor.orR, + BRUOpType.getBranchType(BRUOpType.blt) -> slt, + BRUOpType.getBranchType(BRUOpType.bltu) -> sltu ) io.out.pred_fail := io.in.pred_branch =/= io.out.branch - io.out.branch := (LookupTree(ALUOpType.getBranchType(op), table) ^ - ALUOpType.isBranchInvert(op)) & valid + io.out.branch := (LookupTree(BRUOpType.getBranchType(op), table) ^ + BRUOpType.isBranchInvert(op)) & valid io.out.target := MuxCase( io.in.pc + 4.U, // 默认顺序运行吧 Seq( diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 8a69f42..041d7ad 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -53,8 +53,8 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { ) val mem_wreg = VecInit( - io.executeStage.inst0.info.fusel===FuType.lsu && io.executeStage.inst0.info.reg_wen, - io.executeStage.inst1.info.fusel===FuType.lsu && io.executeStage.inst1.info.reg_wen + io.executeStage.inst0.info.fusel === FuType.lsu && io.executeStage.inst0.info.reg_wen, + io.executeStage.inst1.info.fusel === FuType.lsu && io.executeStage.inst1.info.reg_wen ) io.ctrl.inst(0).mem_wreg := mem_wreg(0) @@ -119,11 +119,11 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { io.memoryStage.inst0.pc := io.executeStage.inst0.pc io.memoryStage.inst0.info := io.executeStage.inst0.info io.memoryStage.inst0.src_info := io.executeStage.inst0.src_info + io.memoryStage.inst0.rd_info.wdata := DontCare io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu + io.memoryStage.inst0.rd_info.wdata(FuType.bru) := io.executeStage.inst0.pc + 4.U io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata - io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U - io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U val has_ex0 = (HasExcInt(io.executeStage.inst0.ex)) && io.executeStage.inst0.info.valid io.memoryStage.inst0.ex := Mux( @@ -144,11 +144,10 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { io.memoryStage.inst1.pc := io.executeStage.inst1.pc io.memoryStage.inst1.info := io.executeStage.inst1.info io.memoryStage.inst1.src_info := io.executeStage.inst1.src_info + io.memoryStage.inst1.rd_info.wdata := DontCare io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata - io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U - io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U val has_ex1 = (HasExcInt(io.executeStage.inst1.ex)) && io.executeStage.inst1.info.valid io.memoryStage.inst1.ex := Mux( diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index a4e2ad9..b81017e 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -70,11 +70,7 @@ class Fu(implicit val config: CpuConfig) extends Module { io.stall_req := io.inst.map(_.info.fusel === FuType.mdu).reduce(_ || _) && !mdu.ready - io.inst(0).result.alu := Mux( - ALUOpType.isBru(io.inst(0).info.op), - io.inst(0).pc + 4.U, - alu(0).io.result - ) + io.inst(0).result.alu := alu(0).io.result io.inst(0).result.mdu := mdu.result io.inst(1).result.alu := alu(1).io.result diff --git a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala index 6b0be0c..7d0d8ea 100644 --- a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala +++ b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala @@ -5,7 +5,7 @@ import chisel3.util._ import cpu.defines.Const._ import cpu._ import cpu.pipeline.decoder.Src12Read -import cpu.defines.ALUOpType +import cpu.defines.BRUOpType import cpu.defines.FuOpType import cpu.defines.FuType import cpu.defines.SignedExtend @@ -61,7 +61,7 @@ class GlobalBranchPredictor( val imm = io.decoder.info.imm io.decoder.branch_inst := io.decoder.info.valid && - FuType.bru === io.decoder.info.fusel && ALUOpType.isBranch(io.decoder.info.op) + FuType.bru === io.decoder.info.fusel && BRUOpType.isBranch(io.decoder.info.op) io.decoder.branch_target := io.decoder.pc + imm // 局部预测模式 @@ -110,7 +110,7 @@ class AdaptiveTwoLevelPredictor( val imm = io.decoder.info.imm io.decoder.branch_inst := io.decoder.info.valid && - FuType.bru === io.decoder.info.fusel && ALUOpType.isBranch(io.decoder.info.op) + FuType.bru === io.decoder.info.fusel && BRUOpType.isBranch(io.decoder.info.op) io.decoder.branch_target := io.decoder.pc + imm val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W))))