From 6d165c916c37a6d415c65c2acf59d9720944d20b Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 20 Nov 2023 15:16:48 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9branch=20ctrl?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../src/pipeline/execute/BranchCtrl.scala | 66 +++++++++---------- .../pipeline/fetch/BranchPredictorUnit.scala | 6 +- chisel/playground/test/src/TestMain.scala | 3 +- 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/BranchCtrl.scala index b943e0e..c935490 100644 --- a/chisel/playground/src/pipeline/execute/BranchCtrl.scala +++ b/chisel/playground/src/pipeline/execute/BranchCtrl.scala @@ -1,35 +1,35 @@ -// package cpu.pipeline.execute +package cpu.pipeline.execute -// import chisel3._ -// import chisel3.util._ -// import cpu.defines._ -// import cpu.defines.Const._ +import chisel3._ +import chisel3.util._ +import cpu.defines._ +import cpu.defines.Const._ -// class BranchCtrl extends Module { -// val io = IO(new Bundle { -// val in = new Bundle { -// val inst_info = Input(new InstInfo()) -// val src_info = Input(new SrcInfo()) -// val pred_branch = Input(Bool()) -// } -// val out = new Bundle { -// val branch = Output(Bool()) -// val pred_fail = Output(Bool()) -// } -// }) -// val src1 = io.in.src_info.src1_data -// val src2 = io.in.src_info.src2_data -// io.out.pred_fail := io.in.pred_branch =/= io.out.branch -// io.out.branch := MuxLookup(io.in.inst_info.op, false.B)( -// Seq( -// EXE_BEQ -> (src1 === src2), -// EXE_BNE -> (src1 =/= src2), -// EXE_BGTZ -> (!src1(31) && (src1 =/= 0.U)), -// EXE_BLEZ -> (src1(31) || src1 === 0.U), -// EXE_BGEZ -> (!src1(31)), -// EXE_BGEZAL -> (!src1(31)), -// EXE_BLTZ -> (src1(31)), -// EXE_BLTZAL -> (src1(31)) -// ) -// ) -// } +class BranchCtrl extends Module { + val io = IO(new Bundle { + val in = new Bundle { + val inst_info = Input(new InstInfo()) + val src_info = Input(new SrcInfo()) + val pred_branch = Input(Bool()) + } + val out = new Bundle { + val branch = Output(Bool()) + val pred_fail = Output(Bool()) + } + }) + val src1 = io.in.src_info.src1_data + val src2 = io.in.src_info.src2_data + val op = io.in.inst_info.op + val is_sub = !ALUOpType.isAdd(op) + val adder = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub + val xor = src1 ^ src2 + val sltu = !adder(XLEN) + val slt = xor(XLEN - 1) ^ sltu + val table = List( + ALUOpType.getBranchType(ALUOpType.beq) -> !xor.orR, + ALUOpType.getBranchType(ALUOpType.blt) -> slt, + ALUOpType.getBranchType(ALUOpType.bltu) -> sltu + ) + io.out.pred_fail := io.in.pred_branch =/= io.out.branch + io.out.branch := Util.LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op) +} diff --git a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala index d4f5c14..9f223c8 100644 --- a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala +++ b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala @@ -7,6 +7,7 @@ import cpu._ import cpu.pipeline.decoder.Src12Read import cpu.defines.ALUOpType import cpu.defines.FuOpType +import cpu.defines.FuType class ExecuteUnitBranchPredictor extends Bundle { val bpuConfig = new BranchPredictorConfig() @@ -21,6 +22,7 @@ class BranchPredictorIO(implicit config: CpuConfig) extends Bundle { val decoder = new Bundle { val inst = Input(UInt(INST_WID.W)) val op = Input(FuOpType()) + val fusel = Input(FuType()) val ena = Input(Bool()) val pc = Input(UInt(PC_WID.W)) val pc_plus4 = Input(UInt(PC_WID.W)) @@ -70,7 +72,7 @@ class GlobalBranchPredictor( val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4) - io.decoder.branch_inst := ALUOpType.isBru(io.decoder.op) && ALUOpType.isBranch(io.decoder.op) + io.decoder.branch_inst := FuType.bru === io.decoder.fusel && ALUOpType.isBranch(io.decoder.op) io.decoder.branch_target := io.decoder.pc_plus4 + Cat( Fill(14, io.decoder.inst(15)), io.decoder.inst(15, 0), @@ -120,7 +122,7 @@ class AdaptiveTwoLevelPredictor( val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4) - io.decoder.branch_inst := ALUOpType.isBru(io.decoder.op) && ALUOpType.isBranch(io.decoder.op) + io.decoder.branch_inst := FuType.bru === io.decoder.fusel && ALUOpType.isBranch(io.decoder.op) io.decoder.branch_target := io.decoder.pc_plus4 + Cat( Fill(14, io.decoder.inst(15)), io.decoder.inst(15, 0), diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala index afa831e..eec08c0 100644 --- a/chisel/playground/test/src/TestMain.scala +++ b/chisel/playground/test/src/TestMain.scala @@ -6,10 +6,11 @@ import cpu.pipeline.decoder.DecoderUnit import cache.ICache import cpu.pipeline.fetch.BranchPredictorUnit import cpu.pipeline.execute.Alu +import cpu.pipeline.execute.BranchCtrl object TestMain extends App { implicit val config = new CpuConfig() - def top = new Alu() + def top = new BranchCtrl() val useMFC = false // use MLIR-based firrtl compiler val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) if (useMFC) {