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fix(csr): 修复例外传递bug

This commit is contained in:
Liphen 2023-11-30 17:56:14 +08:00
parent 6728817004
commit 69f5974661
2 changed files with 50 additions and 27 deletions
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15
chisel/playground/src/pipeline/execute/Csr.scala
View File

@ -243,7 +243,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
// Fix Mip/Sip write // Fix Mip/Sip write
val fixMapping = Map( val fixMapping = Map(
MaskedRegMap(Mip, mipReg.asUInt, mipFixMask) MaskedRegMap(Mip, mipReg.asUInt, mipFixMask)
// MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) TODO // MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) //TODO
) )
val rdataDummy = Wire(UInt(XLEN.W)) val rdataDummy = Wire(UInt(XLEN.W))
MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata) MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata)
@ -303,10 +303,11 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
ret_target := mepc(VADDR_WID - 1, 0) ret_target := mepc(VADDR_WID - 1, 0)
} }
io.decoderUnit.priv_mode := priv_mode io.decoderUnit.priv_mode := priv_mode
io.executeUnit.out.ex := io.executeUnit.in.ex io.executeUnit.out.ex := io.executeUnit.in.ex
io.executeUnit.out.ex.exception(illegalInstr) := (illegal_addr || illegal_access) && wen io.executeUnit.out.ex.exception(illegalInstr) :=
io.executeUnit.out.rdata := rdata (illegal_addr || illegal_access) && wen | io.executeUnit.in.ex.exception(illegalInstr)
io.memoryUnit.out.flush := has_exc_int || ret io.executeUnit.out.rdata := rdata
io.memoryUnit.out.flush_pc := Mux(has_exc_int, trap_target, ret_target) io.memoryUnit.out.flush := has_exc_int || ret
io.memoryUnit.out.flush_pc := Mux(has_exc_int, trap_target, ret_target)
} }

62
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -53,20 +53,26 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr && val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
!(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) !(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
io.csr.in.valid := (csr_sel0 || csr_sel1) io.csr.in.valid := (csr_sel0 || csr_sel1)
io.csr.in.inst_info := Mux( io.csr.in.inst_info := MuxCase(
csr_sel0 && !csr_sel1, 0.U.asTypeOf(new InstInfo()),
io.executeStage.inst0.inst_info, Seq(
io.executeStage.inst1.inst_info csr_sel0 -> io.executeStage.inst0.inst_info,
csr_sel1 -> io.executeStage.inst1.inst_info
)
) )
io.csr.in.src_info := Mux( io.csr.in.src_info := MuxCase(
csr_sel0 && !csr_sel1, 0.U.asTypeOf(new SrcInfo()),
io.executeStage.inst0.src_info, Seq(
io.executeStage.inst1.src_info csr_sel0 -> io.executeStage.inst0.src_info,
csr_sel1 -> io.executeStage.inst1.src_info
)
) )
io.csr.in.ex := Mux( io.csr.in.ex := MuxCase(
csr_sel0 && !csr_sel1, 0.U.asTypeOf(new ExceptionInfo()),
io.executeStage.inst0.ex, Seq(
io.executeStage.inst1.ex csr_sel0 -> io.executeStage.inst0.ex,
csr_sel1 -> io.executeStage.inst1.ex
)
) )
// input accessMemCtrl // input accessMemCtrl
@ -130,10 +136,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)( val has_ex0 =
Seq( (io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.inst_info.valid
FuType.lsu -> accessMemCtrl.inst(0).ex.out, io.memoryStage.inst0.ex := Mux(
FuType.csr -> io.csr.out.ex has_ex0,
io.executeStage.inst0.ex,
MuxLookup(io.executeStage.inst0.inst_info.fusel, io.executeStage.inst0.ex)(
Seq(
FuType.alu -> fu.inst(0).ex.out,
FuType.mdu -> fu.inst(0).ex.out,
FuType.lsu -> accessMemCtrl.inst(0).ex.out,
FuType.csr -> io.csr.out.ex
)
) )
) )
@ -144,10 +158,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)( val has_ex1 =
Seq( (io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.inst_info.valid
FuType.lsu -> accessMemCtrl.inst(1).ex.out, io.memoryStage.inst1.ex := Mux(
FuType.csr -> io.csr.out.ex has_ex1,
io.executeStage.inst1.ex,
MuxLookup(io.executeStage.inst1.inst_info.fusel, io.executeStage.inst1.ex)(
Seq(
FuType.alu -> fu.inst(1).ex.out,
FuType.mdu -> fu.inst(1).ex.out,
FuType.lsu -> accessMemCtrl.inst(1).ex.out,
FuType.csr -> io.csr.out.ex
)
) )
) )