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perf(idu): 增加保留指令的tval

This commit is contained in:
Liphen 2024-01-02 15:06:08 +08:00
parent 287cc5479d
commit 69e8b45484
3 changed files with 29 additions and 24 deletions
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18
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -123,8 +123,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.ex.exception.map(_ := false.B)
io.executeStage.inst0.ex.exception(illegalInstr) := !info(0).inst_legal
io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err
io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(1, 0).orR ||
io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR ||
io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
info(0).op === CSROpType.jmp && info(0).fusel === FuType.csr
io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
@ -136,8 +136,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.ex.tval := MuxCase(
0.U,
Seq(
pc(0)(1, 0).orR -> pc(0),
(io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(0),
!info(0).inst_legal -> info(0).inst,
(io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
)
)
@ -165,8 +166,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.exception.map(_ := false.B)
io.executeStage.inst1.ex.exception(illegalInstr) := !info(1).inst_legal
io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR ||
io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR ||
io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
info(1).op === CSROpType.jmp && info(1).fusel === FuType.csr
io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
@ -179,8 +180,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.tval := MuxCase(
0.U,
Seq(
pc(1)(1, 0).orR -> pc(1),
(io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(1),
!info(1).inst_legal -> info(1).inst,
(io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
)
)

8
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -148,8 +148,8 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
)
)
io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(1, 0).orR
when(io.fetchUnit.flush && io.fetchUnit.target(1, 0).orR) {
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
when(io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR) {
io.memoryStage.inst0.ex.tval := io.fetchUnit.target
}
@ -172,8 +172,8 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
)
)
io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(1, 0).orR
when(io.fetchUnit.flush && io.fetchUnit.target(1, 0).orR) {
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
when(io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR) {
io.memoryStage.inst1.ex.tval := io.fetchUnit.target
}

27
chisel/playground/src/pipeline/execute/fu/Csr.scala
View File

@ -55,6 +55,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val memoryUnit = new CsrMemoryUnit()
})
// 目前的csr只支持64位
assert(XLEN == 64, "XLEN must be 64")
/* CSR寄存器定义 */
// Machine Information Registers
val mvendorid = RegInit(UInt(XLEN.W), 0.U) // 厂商ID
@ -65,6 +68,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
// Machine Trap Setup
val mstatus_init = Wire(new Mstatus())
mstatus_init := 0.U.asTypeOf(new Mstatus())
mstatus_init.sxl := 2.U
mstatus_init.uxl := 2.U
val mstatus = RegInit(UInt(XLEN.W), mstatus_init.asUInt) // 状态寄存器
val misa_init = Wire(new Misa())
@ -90,9 +94,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val mcause = RegInit(UInt(XLEN.W), 0.U) // 异常原因寄存器
val mtval = RegInit(UInt(XLEN.W), 0.U) // 异常值寄存器
val mipWire = WireInit(0.U.asTypeOf(new Interrupt))
val mipReg = RegInit(0.U(64.W))
val mipReg = RegInit(UInt(XLEN.W), 0.U)
val mipFixMask = "h77f".U(64.W)
val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt) // 中断挂起寄存器
val mip = mipWire.asUInt | mipReg // 中断挂起寄存器
// Machine Memory Protection
val pmpcfg0 = RegInit(UInt(XLEN.W), 0.U)
@ -184,7 +188,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
MaskedRegMap(Sepc, sepc),
MaskedRegMap(Scause, scause),
MaskedRegMap(Stval, stval),
MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
MaskedRegMap(Sip, mip, sipMask, MaskedRegMap.Unwritable, sipMask),
// Supervisor Protection and Translation
MaskedRegMap(Satp, satp),
// Machine Information Registers
@ -205,7 +209,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
MaskedRegMap(Mepc, mepc),
MaskedRegMap(Mcause, mcause),
MaskedRegMap(Mtval, mtval),
MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable),
MaskedRegMap(Mip, mip, 0.U, MaskedRegMap.Unwritable),
// Machine Memory Protection
// MaskedRegMap(Pmpcfg0, pmpcfg0),
// MaskedRegMap(Pmpcfg1, pmpcfg1),
@ -231,8 +235,8 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
mipWire.e.m := meip
mipWire.s.m := msip
val seip = meip
val mip_has_interrupt = WireInit(mip)
mip_has_interrupt.e.s := mip.e.s | seip
val mip_has_interrupt = WireInit(mip.asTypeOf(new Interrupt()))
mip_has_interrupt.e.s := mip.asTypeOf(new Interrupt).e.s | seip
val ideleg = (mideleg & mip_has_interrupt.asUInt)
def priviledgedEnableDetect(x: Bool): Bool = Mux(
@ -270,7 +274,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
CSROpType.wrt -> src1,
CSROpType.set -> (rdata | src1),
CSROpType.clr -> (rdata & ~src1),
CSROpType.wrti -> csri, //TODO: csri --> src2
CSROpType.wrti -> csri,
CSROpType.seti -> (rdata | csri),
CSROpType.clri -> (rdata & ~csri)
)
@ -287,13 +291,12 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
MaskedRegMap.generate(mapping, addr, rdata, wen, wdata)
val illegal_addr = MaskedRegMap.isIllegalAddr(mapping, addr)
val write_satp = (addr === Satp.U) && write
// Fix Mip/Sip write
val fixMapping = Map(
MaskedRegMap(Mip, mipReg.asUInt, mipFixMask),
MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask)
val ipMapping = Map(
MaskedRegMap(Mip, mipReg, mipFixMask),
MaskedRegMap(Sip, mipReg, sipMask, MaskedRegMap.NoSideEffect, sipMask)
)
val rdataDummy = Wire(UInt(XLEN.W))
MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen, wdata)
MaskedRegMap.generate(ipMapping, addr, rdataDummy, wen, wdata)
// CSR inst decode
val ret = Wire(Bool())