From 68055ff7451be2e923b9bbc7bbc3c8332197cd84 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 24 Nov 2023 16:54:41 +0800 Subject: [PATCH] =?UTF-8?q?fix(jump=20ctrl):=20=E4=BF=AE=E6=94=B9jump=20ta?= =?UTF-8?q?rget=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../src/pipeline/decoder/DecoderUnit.scala | 22 +++++++------- .../src/pipeline/decoder/JumpCtrl.scala | 29 +++++++++---------- 2 files changed, 25 insertions(+), 26 deletions(-) diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index 4a92043..69d276d 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -74,17 +74,17 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti } io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go - io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr - io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr - io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr - io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr - forwardCtrl.in.forward := io.forward - forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题 - jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go - jumpCtrl.in.decoded_inst0 := decoder(0).io.out.inst_info - jumpCtrl.in.forward := io.forward - jumpCtrl.in.pc := io.instFifo.inst(0).pc - jumpCtrl.in.reg1_data := io.regfile(0).src1.rdata + io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr + io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr + io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr + io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr + forwardCtrl.in.forward := io.forward + forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题 + jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go + jumpCtrl.in.inst_info := decoder(0).io.out.inst_info + jumpCtrl.in.forward := io.forward + jumpCtrl.in.pc := io.instFifo.inst(0).pc + jumpCtrl.in.src_info := io.executeStage.inst0.src_info val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala index 11142dc..60b185f 100644 --- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala +++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala @@ -10,11 +10,11 @@ import cpu.CpuConfig class JumpCtrl(implicit val config: CpuConfig) extends Module { val io = IO(new Bundle { val in = Input(new Bundle { - val allow_to_go = Bool() - val pc = UInt(PC_WID.W) - val decoded_inst0 = new InstInfo() - val reg1_data = UInt(DATA_WID.W) - val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) + val allow_to_go = Bool() + val pc = UInt(PC_WID.W) + val inst_info = new InstInfo() + val src_info = new SrcInfo() + val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) }) val out = Output(new Bundle { val jump_inst = Bool() @@ -24,27 +24,26 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module { }) }) - val op = io.in.decoded_inst0.op + val op = io.in.inst_info.op val jump_inst = VecInit(ALUOpType.jal).contains(op) val jump_register_inst = VecInit(ALUOpType.jalr).contains(op) io.out.jump_inst := jump_inst || jump_register_inst io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register) if (config.decoderNum == 2) { io.out.jump_register := jump_register_inst && - ((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) || - (io.in.forward(1).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).exe.waddr) || - (io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr) || - (io.in.forward(1).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).mem.waddr)) + ((io.in.forward(0).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).exe.waddr) || + (io.in.forward(1).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(1).exe.waddr) || + (io.in.forward(0).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).mem.waddr) || + (io.in.forward(1).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(1).mem.waddr)) } else { io.out.jump_register := jump_register_inst && - ((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) || - (io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr)) + ((io.in.forward(0).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).exe.waddr) || + (io.in.forward(0).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).mem.waddr)) } - val pc_plus_4 = io.in.pc + 4.U(PC_WID.W) io.out.jump_target := Mux( jump_inst, - Cat(pc_plus_4(31, 28), io.in.decoded_inst0.inst(25, 0), 0.U(2.W)), - io.in.reg1_data + io.in.src_info.src1_data + io.in.src_info.src2_data, + io.in.src_info.src1_data ) }