diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index bd4a0e8..b38e4ab 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -36,7 +36,10 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   val fu            = Module(new Fu()).io
   val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
 
-  val valid = VecInit(io.executeStage.inst0.inst_info.valid, io.executeStage.inst1.inst_info.valid)
+  val valid = VecInit(
+    io.executeStage.inst0.inst_info.valid && io.ctrl.allow_to_go,
+    io.executeStage.inst1.inst_info.valid && io.ctrl.allow_to_go
+  )
 
   io.ctrl.inst(0).mem_wreg  := io.executeStage.inst0.inst_info.mem_wreg
   io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
@@ -46,10 +49,10 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
   val csr_sel0 = valid(0) && io.executeStage.inst0.inst_info.fusel === FuType.csr &&
-    !(io.executeStage.inst0.ex.exception.asUInt.orR|| io.executeStage.inst0.ex.interrupt.asUInt.orR)
+    !(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR)
   val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
-    !(io.executeStage.inst1.ex.exception.asUInt.orR|| io.executeStage.inst1.ex.interrupt.asUInt.orR)
-  io.csr.in.valid := csr_sel0 || csr_sel1
+    !(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
+  io.csr.in.valid := (csr_sel0 || csr_sel1)
   io.csr.in.inst_info := Mux(
     csr_sel0 && !csr_sel1,
     io.executeStage.inst0.inst_info,
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index a8ddaaa..05634de 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -65,14 +65,22 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid &&
     !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
 
-  io.csr.in.inst(0).pc        := io.writeBackStage.inst0.pc
-  io.csr.in.inst(0).ex        := io.writeBackStage.inst0.ex
-  io.csr.in.inst(0).inst_info := io.writeBackStage.inst0.inst_info
-  io.csr.in.inst(1).pc        := io.writeBackStage.inst1.pc
-  io.csr.in.inst(1).ex        := io.writeBackStage.inst1.ex
-  io.csr.in.inst(1).inst_info := io.writeBackStage.inst1.inst_info
+  io.csr.in.inst(0).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.pc, 0.U)
+  io.csr.in.inst(0).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo()))
+  io.csr.in.inst(0).inst_info := Mux(
+    io.ctrl.allow_to_go,
+    io.writeBackStage.inst0.inst_info,
+    0.U.asTypeOf(new InstInfo())
+  )
+  io.csr.in.inst(1).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.pc, 0.U)
+  io.csr.in.inst(1).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.ex, 0.U.asTypeOf(new ExceptionInfo()))
+  io.csr.in.inst(1).inst_info := Mux(
+    io.ctrl.allow_to_go,
+    io.writeBackStage.inst1.inst_info,
+    0.U.asTypeOf(new InstInfo())
+  )
 
-  io.fetchUnit.flush    := io.csr.out.flush
+  io.fetchUnit.flush    := io.csr.out.flush && io.ctrl.allow_to_go
   io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
 
   io.ctrl.flush_req := io.fetchUnit.flush