From 66b42d13f441c485cc23392495b50fdcdbcdb4ff Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 23 Nov 2023 16:38:49 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8F=AF=E4=BB=A5=E5=AE=9E=E7=8E=B0=E5=B7=AE?= =?UTF-8?q?=E5=88=86=E6=B5=8B=E8=AF=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/Makefile | 3 ++- chisel/difftest | 2 +- chisel/playground/src/CpuConfig.scala | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/chisel/Makefile b/chisel/Makefile index 792560a..d5e0796 100644 --- a/chisel/Makefile +++ b/chisel/Makefile @@ -10,7 +10,8 @@ verilog: mill -i __.test.runMain Elaborate -td $(BUILD_DIR) func: - # cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR) + $(MAKE) verilog + cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR) cd $(DIFF_WORK_DIR) && make func test: diff --git a/chisel/difftest b/chisel/difftest index 1f6c6a6..219f3b9 160000 --- a/chisel/difftest +++ b/chisel/difftest @@ -1 +1 @@ -Subproject commit 1f6c6a632c18a0fd1daf6b1c09a8fa56717b7679 +Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5 diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala index 7b2bd12..d28f937 100644 --- a/chisel/playground/src/CpuConfig.scala +++ b/chisel/playground/src/CpuConfig.scala @@ -11,7 +11,7 @@ case class CpuConfig( val hasSMode: Boolean = false, // 是否有S模式 val hasUMode: Boolean = false, // 是否有U模式 // 模块配置 - val hasCommitBuffer: Boolean = false, // 是否有提交缓存 + val hasCommitBuffer: Boolean = true, // 是否有提交缓存 val decoderNum: Int = 2, // 同时访问寄存器的指令数 val commitNum: Int = 2, // 同时提交的指令数 val fuNum: Int = 2, // 功能单元数