diff --git a/chisel/Makefile b/chisel/Makefile
index 792560a..d5e0796 100644
--- a/chisel/Makefile
+++ b/chisel/Makefile
@@ -10,7 +10,8 @@ verilog:
 	mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
 
 func:
-	# cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
+	$(MAKE) verilog
+	cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
 	cd $(DIFF_WORK_DIR) && make func
 
 test:
diff --git a/chisel/difftest b/chisel/difftest
index 1f6c6a6..219f3b9 160000
--- a/chisel/difftest
+++ b/chisel/difftest
@@ -1 +1 @@
-Subproject commit 1f6c6a632c18a0fd1daf6b1c09a8fa56717b7679
+Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5
diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala
index 7b2bd12..d28f937 100644
--- a/chisel/playground/src/CpuConfig.scala
+++ b/chisel/playground/src/CpuConfig.scala
@@ -11,7 +11,7 @@ case class CpuConfig(
   val hasSMode: Boolean = false, // 是否有S模式
   val hasUMode: Boolean = false, // 是否有U模式
   // 模块配置
-  val hasCommitBuffer: Boolean = false, // 是否有提交缓存
+  val hasCommitBuffer: Boolean = true, // 是否有提交缓存
   val decoderNum:      Int     = 2, // 同时访问寄存器的指令数
   val commitNum:       Int     = 2, // 同时提交的指令数
   val fuNum:           Int     = 2, // 功能单元数