From 66420825a18dc173a526d481b89408652240ec8a Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 28 Nov 2023 16:34:09 +0800 Subject: [PATCH] =?UTF-8?q?fix(csr):=20=E5=A2=9E=E5=8A=A0m=20info=E5=AF=84?= =?UTF-8?q?=E5=AD=98=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/Csr.scala | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index 3dd7768..a4c8c71 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -135,11 +135,12 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { // MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask), // // Supervisor Protection and Translation // MaskedRegMap(Satp, satp), - // // Machine Information Registers - // MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable), - // MaskedRegMap(Marchid, marchid, 0.U, MaskedRegMap.Unwritable), - // MaskedRegMap(Mimpid, mimpid, 0.U, MaskedRegMap.Unwritable), - // MaskedRegMap(Mhartid, mhartid, 0.U, MaskedRegMap.Unwritable), + + // Machine Information Registers + MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable), + MaskedRegMap(Marchid, marchid, 0.U, MaskedRegMap.Unwritable), + MaskedRegMap(Mimpid, mimpid, 0.U, MaskedRegMap.Unwritable), + MaskedRegMap(Mhartid, mhartid, 0.U, MaskedRegMap.Unwritable), // Machine Trap Setup // MaskedRegMap(Mstatus, mstatus, "hffffffffffffffee".U, (x=>{printf("mstatus write: %x time: %d\n", x, GTimer()); x})), MaskedRegMap(Mstatus, mstatus, "hffffffffffffffff".U(64.W), mstatusUpdateSideEffect), @@ -239,9 +240,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { io.executeUnit.out.ex.exception(illegalInstr) := (illegal_addr || illegal_access) && wen io.executeUnit.out.rdata := rdata - io.decoderUnit.priv_mode := priv_mode + io.decoderUnit.priv_mode := priv_mode - io.memoryUnit.out.flush := exc.exception.asUInt.orR || exc.interrupt.asUInt.orR + io.memoryUnit.out.flush := exc.exception.asUInt.orR || exc.interrupt.asUInt.orR io.memoryUnit.out.flush_pc := mtvec }