yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

feat: 增加MOU用于处理fence相关指令

This commit is contained in:
Liphen 2023-12-01 16:35:59 +08:00
parent 005880f152
commit 651f8319dd
7 changed files with 50 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
chisel/playground/src/Core.scala
View File

@ -95,10 +95,10 @@ class Core(implicit val config: CpuConfig) extends Module {
decoderUnit.csr <> csr.decoderUnit
decoderUnit.executeStage <> executeStage.decoderUnit
executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req ||
executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush ||
ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
!ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go
executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req ||
executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush ||
(ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) ||
(ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go)
executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go
@ -137,8 +137,7 @@ class Core(implicit val config: CpuConfig) extends Module {
io.debug <> writeBackUnit.debug
io.inst.fence := executeUnit.executeStage.inst0.info.fusel === FuType.mou &&
executeUnit.executeStage.inst0.info.op === MOUOpType.fencei
io.inst.fence := false.B
io.data.fence := false.B
io.inst.req := !instFifo.full && !reset.asBool
io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go

8
chisel/playground/src/ctrl/Ctrl.scala
View File

@ -31,12 +31,12 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
io.decoderUnit.allow_to_go := !(lw_stall || longest_stall)
io.executeUnit.allow_to_go := !longest_stall
io.memoryUnit.allow_to_go := !longest_stall
io.writeBackUnit.allow_to_go := !longest_stall || io.memoryUnit.flush_req
io.writeBackUnit.allow_to_go := !longest_stall || io.memoryUnit.flush
io.fetchUnit.do_flush := false.B
io.decoderUnit.do_flush := io.memoryUnit.flush_req || io.executeUnit.branch || io.decoderUnit.branch
io.executeUnit.do_flush := io.memoryUnit.flush_req || io.executeUnit.branch
io.memoryUnit.do_flush := io.memoryUnit.flush_req
io.decoderUnit.do_flush := io.memoryUnit.flush || io.executeUnit.flush || io.decoderUnit.branch
io.executeUnit.do_flush := io.memoryUnit.flush || io.executeUnit.flush
io.memoryUnit.do_flush := io.memoryUnit.flush
io.writeBackUnit.do_flush := false.B
io.executeUnit.fu.allow_to_go := io.memoryUnit.allow_to_go

4
chisel/playground/src/defines/Bundles.scala
View File

@ -85,7 +85,7 @@ class ExecuteFuCtrl extends Bundle {
class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
val inst = Output(Vec(config.fuNum, new MemRead()))
val fu_stall = Output(Bool())
val branch = Output(Bool())
val flush = Output(Bool())
val allow_to_go = Input(Bool())
val do_flush = Input(Bool())
@ -94,7 +94,7 @@ class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
}
class MemoryCtrl extends Bundle {
val flush_req = Output(Bool())
val flush = Output(Bool())
val allow_to_go = Input(Bool())
val do_flush = Input(Bool())

2
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -57,7 +57,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.info.mem_wreg
io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
io.ctrl.branch := io.fetchUnit.flush
io.ctrl.flush := io.fetchUnit.flush
io.csr.in.valid := is_csr.asUInt.orR
io.csr.in.info := MuxCase(

10
chisel/playground/src/pipeline/execute/Fu.scala
View File

@ -38,6 +38,10 @@ class Fu(implicit val config: CpuConfig) extends Module {
val alu = Seq.fill(config.decoderNum)(Module(new Alu()))
val branchCtrl = Module(new BranchCtrl()).io
val mou = Module(new Mou()).io
mou.in.info := io.inst(0).info
mou.in.pc := io.inst(0).pc
branchCtrl.in.pc := io.inst(0).pc
branchCtrl.in.info := io.inst(0).info
@ -46,8 +50,10 @@ class Fu(implicit val config: CpuConfig) extends Module {
branchCtrl.in.jump_regiser := io.branch.jump_regiser
branchCtrl.in.branch_target := io.branch.branch_target
io.branch.branch := branchCtrl.out.branch
io.branch.flush := (branchCtrl.out.pred_fail || io.branch.jump_regiser)
io.branch.target := branchCtrl.out.target
val branchCtrl_flush = (branchCtrl.out.pred_fail || io.branch.jump_regiser)
io.branch.flush := branchCtrl_flush || mou.out.flush
io.branch.target := Mux(branchCtrl_flush, branchCtrl.out.target, mou.out.target)
for (i <- 0 until (config.fuNum)) {
alu(i).io.info := io.inst(i).info

31
chisel/playground/src/pipeline/execute/Mou.scala Normal file
View File

@ -0,0 +1,31 @@
package cpu.pipeline.execute
import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
class Mou extends Module {
val io = IO(new Bundle {
val in = Input(new Bundle {
val info = new InstInfo()
val pc = UInt(PC_WID.W)
})
val out = Output(new Bundle {
val flush = Bool()
val target = UInt(PC_WID.W)
})
})
val valid = io.in.info.valid
val fence_i = valid && io.in.info.fusel === FuType.mou && io.in.info.op === MOUOpType.fencei
// TODO:增加其他fence指令时只要在后面加就行
io.out.flush := fence_i
io.out.target := MuxCase(
io.in.pc + 4.U,
Seq(
fence_i -> (io.in.pc + 4.U)
)
)
}

2
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -83,5 +83,5 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.fetchUnit.flush := io.csr.out.flush && io.ctrl.allow_to_go
io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
io.ctrl.flush_req := io.fetchUnit.flush
io.ctrl.flush := io.fetchUnit.flush
}