diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index a023d66..b596f99 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -7,7 +7,6 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class ExceptionInfo extends Bundle {
-  val flush_req = Bool()
   val excode    = Vec(EXCODE_WID, Bool())
   val interrupt = Vec(INT_WID, Bool())
   val tval      = UInt(XLEN.W)
diff --git a/chisel/playground/src/defines/CsrBundles.scala b/chisel/playground/src/defines/CsrBundles.scala
index ea52f9c..916a132 100644
--- a/chisel/playground/src/defines/CsrBundles.scala
+++ b/chisel/playground/src/defines/CsrBundles.scala
@@ -81,6 +81,25 @@ class Mie extends Bundle {
   val blank6 = UInt(2.W)
 }
 
+class Satp extends Bundle {
+  val mode = UInt(4.W)
+  val asid = UInt(16.W)
+  val ppn  = UInt(44.W)
+}
+
+class Priv extends Bundle {
+  val m = Output(Bool())
+  val h = Output(Bool())
+  val s = Output(Bool())
+  val u = Output(Bool())
+}
+
+class Interrupt extends Bundle {
+  val e = new Priv()
+  val t = new Priv()
+  val s = new Priv()
+}
+
 object Priv {
   def u       = "b00".U
   def s       = "b01".U
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index 581d00f..743b66c 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -127,9 +127,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     forwardCtrl.out.inst(0).src2.rdata,
     decoder(0).io.out.inst_info.imm
   )
-  io.executeStage.inst0.ex.flush_req    := io.executeStage.inst0.ex.excode.asUInt.orR
-  io.executeStage.inst0.ex.excode.map(_ := false.B)
-
+  io.executeStage.inst0.ex.excode.map(_                := false.B)
   io.executeStage.inst0.ex.excode(illegalInstr)        := !inst_info(0).inst_valid
   io.executeStage.inst0.ex.excode(instrAccessFault)    := io.instFifo.inst(0).acc_err
   io.executeStage.inst0.ex.excode(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
@@ -167,9 +165,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
       forwardCtrl.out.inst(1).src2.rdata,
       decoder(1).io.out.inst_info.imm
     )
-    io.executeStage.inst1.ex.flush_req    := io.executeStage.inst1.ex.excode.asUInt.orR
-    io.executeStage.inst1.ex.excode.map(_ := false.B)
-
+    io.executeStage.inst1.ex.excode.map(_                := false.B)
     io.executeStage.inst1.ex.excode(illegalInstr)        := !inst_info(1).inst_valid
     io.executeStage.inst1.ex.excode(instrAccessFault)    := io.instFifo.inst(1).acc_err
     io.executeStage.inst1.ex.excode(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala
index 437690d..9d785c6 100644
--- a/chisel/playground/src/pipeline/execute/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/Csr.scala
@@ -4,9 +4,8 @@ import chisel3._
 import chisel3.util._
 import cpu.defines._
 import cpu.defines.Const._
-import cpu.pipeline.memory.CsrInfo
 import cpu.CpuConfig
-import cpu.pipeline.decoder.CsrDecoderUnit
+import chisel3.util.experimental.BoringUtils
 
 class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
@@ -26,34 +25,36 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
 
 class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
-    val inst_info  = Vec(config.fuNum, new InstInfo())
-    val mtc0_wdata = UInt(DATA_WID.W)
+    val valid     = Vec(config.fuNum, Bool())
+    val inst_info = Vec(config.fuNum, new InstInfo())
+    val src_info  = Vec(config.fuNum, new SrcInfo())
+    val wdata     = UInt(DATA_WID.W)
   })
   val out = Output(new Bundle {
-    val csr_rdata = Vec(config.fuNum, UInt(DATA_WID.W))
-    val debug     = Output(new CsrInfo())
+    val rdata    = Vec(config.fuNum, UInt(DATA_WID.W))
+    val trap_ill = Bool()
   })
 }
 
-class Csr(implicit val config: CpuConfig) extends Module {
+class CsrDecoderUnit extends Bundle {
+  val priv_mode = Output(Priv())
+  val irq       = Output(Bool())
+  val irq_type  = Output(UInt(4.W))
+}
+
+class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   val io = IO(new Bundle {
     val ext_int = Input(UInt(EXT_INT_WID.W))
     val ctrl = Input(new Bundle {
       val exe_stall = Bool()
       val mem_stall = Bool()
     })
-    val decoderUnit = Output(new CsrDecoderUnit())
+    val decoderUnit = new CsrDecoderUnit()
     val executeUnit = new CsrExecuteUnit()
     val memoryUnit  = new CsrMemoryUnit()
   })
-  // 优先使用inst0的信息
-  val ex_sel    = io.memoryUnit.in.inst(0).ex.flush_req || !io.memoryUnit.in.inst(1).ex.flush_req
-  val pc        = Mux(ex_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
-  val ex        = Mux(ex_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
-  val exe_op    = io.executeUnit.in.inst_info(0).op
-  val exe_stall = io.ctrl.exe_stall
-  val mem_stall = io.ctrl.mem_stall
 
+  /* CSR寄存器定义 */
   val cycle = RegInit(0.U(XLEN.W)) // 时钟周期计数器
 
   val instret = RegInit(0.U(XLEN.W)) // 指令计数器
@@ -66,23 +67,175 @@ class Csr(implicit val config: CpuConfig) extends Module {
   val mstatus_init = Wire(new Mstatus())
   mstatus_init     := 0.U.asTypeOf(new Mstatus())
   mstatus_init.uxl := 2.U
-  val mstatus   = RegInit(mstatus_init) // 状态寄存器
+  val mstatus   = RegInit(mstatus_init.asUInt) // 状态寄存器
   val misa_init = Wire(new Misa())
   misa_init            := 0.U.asTypeOf(new Misa())
   misa_init.mxl        := 2.U
   misa_init.extensions := "h101100".U
-  val misa       = RegInit(misa_init) // ISA寄存器
-  val mie        = RegInit(0.U.asTypeOf(new Mie())) // 中断使能寄存器
-  val mtvec      = RegInit(0.U.asTypeOf(new Mtvec())) // 中断向量基址寄存器
+  val misa       = RegInit(misa_init.asUInt) // ISA寄存器
+  val mie        = RegInit(0.U(XLEN.W)) // 中断使能寄存器
+  val mtvec      = RegInit(0.U(XLEN.W)) // 中断向量基址寄存器
   val mcounteren = RegInit(0.U(XLEN.W)) // 计数器使能寄存器
   val mscratch   = RegInit(0.U(XLEN.W)) // 临时寄存器
   val mepc       = RegInit(0.U(XLEN.W)) // 异常程序计数器
-  val mcause     = RegInit(0.U.asTypeOf(new Mcause())) // 异常原因寄存器
+  val mcause     = RegInit(0.U(XLEN.W)) // 异常原因寄存器
   val mtval      = RegInit(0.U(XLEN.W)) // 异常值寄存器
-  val mip        = RegInit(0.U.asTypeOf(new Mip())) // 中断挂起寄存器
+  val mipWire    = WireInit(0.U.asTypeOf(new Interrupt))
+  val mipReg     = RegInit(0.U(64.W))
+  val mipFixMask = "h77f".U(64.W)
+  val mip        = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt) // 中断挂起寄存器
   val mcycle     = cycle // 时钟周期计数器
   val minstret   = instret // 指令计数器
 
   val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器
   val tdata1  = RegInit(0.U(XLEN.W)) // 跟踪寄存器数据1寄存器
+
+  // Side Effect
+  def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
+    val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
+    val mstatusNew = Cat(mstatusOld.fs === "b11".U, mstatus(XLEN - 2, 0))
+    mstatusNew
+  }
+
+  // CSR reg map
+  val mapping = Map(
+    // User Trap Setup
+    // MaskedRegMap(Ustatus, ustatus),
+    // MaskedRegMap(Uie, uie, 0.U, MaskedRegMap.Unwritable),
+    // MaskedRegMap(Utvec, utvec),
+
+    // User Trap Handling
+    // MaskedRegMap(Uscratch, uscratch),
+    // MaskedRegMap(Uepc, uepc),
+    // MaskedRegMap(Ucause, ucause),
+    // MaskedRegMap(Utval, utval),
+    // MaskedRegMap(Uip, uip),
+
+    // User Floating-Point CSRs (not implemented)
+    // MaskedRegMap(Fflags, fflags),
+    // MaskedRegMap(Frm, frm),
+    // MaskedRegMap(Fcsr, fcsr),
+
+    // User Counter/Timers
+    // MaskedRegMap(Cycle, cycle),
+    // MaskedRegMap(Time, time),
+    // MaskedRegMap(Instret, instret),
+
+    // // Supervisor Trap Setup TODO
+    // MaskedRegMap(Sstatus, mstatus, sstatusWmask, mstatusUpdateSideEffect, sstatusRmask),
+    // // MaskedRegMap(Sedeleg, Sedeleg),
+    // // MaskedRegMap(Sideleg, Sideleg),
+    // MaskedRegMap(Sie, mie, sieMask, MaskedRegMap.NoSideEffect, sieMask),
+    // MaskedRegMap(Stvec, stvec),
+    // MaskedRegMap(Scounteren, scounteren),
+    // // Supervisor Trap Handling
+    // MaskedRegMap(Sscratch, sscratch),
+    // MaskedRegMap(Sepc, sepc),
+    // MaskedRegMap(Scause, scause),
+    // MaskedRegMap(Stval, stval),
+    // MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
+    // // Supervisor Protection and Translation
+    // MaskedRegMap(Satp, satp),
+    // // Machine Information Registers
+    // MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable),
+    // MaskedRegMap(Marchid, marchid, 0.U, MaskedRegMap.Unwritable),
+    // MaskedRegMap(Mimpid, mimpid, 0.U, MaskedRegMap.Unwritable),
+    // MaskedRegMap(Mhartid, mhartid, 0.U, MaskedRegMap.Unwritable),
+    // Machine Trap Setup
+    // MaskedRegMap(Mstatus, mstatus, "hffffffffffffffee".U, (x=>{printf("mstatus write: %x time: %d\n", x, GTimer()); x})),
+    MaskedRegMap(Mstatus, mstatus, "hffffffffffffffff".U(64.W), mstatusUpdateSideEffect),
+    MaskedRegMap(Misa, misa), // now MXL, EXT is not changeable
+    // MaskedRegMap(Medeleg, medeleg, "hbbff".U(64.W)), TODO
+    // MaskedRegMap(Mideleg, mideleg, "h222".U(64.W)),
+    MaskedRegMap(Mie, mie),
+    MaskedRegMap(Mtvec, mtvec),
+    MaskedRegMap(Mcounteren, mcounteren),
+    // Machine Trap Handling
+    MaskedRegMap(Mscratch, mscratch),
+    MaskedRegMap(Mepc, mepc),
+    MaskedRegMap(Mcause, mcause),
+    MaskedRegMap(Mtval, mtval),
+    MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable)
+    // // Machine Memory Protection TODO
+    // MaskedRegMap(Pmpcfg0, pmpcfg0),
+    // MaskedRegMap(Pmpcfg1, pmpcfg1),
+    // MaskedRegMap(Pmpcfg2, pmpcfg2),
+    // MaskedRegMap(Pmpcfg3, pmpcfg3),
+    // MaskedRegMap(PmpaddrBase + 0, pmpaddr0, pmpaddrWmask),
+    // MaskedRegMap(PmpaddrBase + 1, pmpaddr1, pmpaddrWmask),
+    // MaskedRegMap(PmpaddrBase + 2, pmpaddr2, pmpaddrWmask),
+    // MaskedRegMap(PmpaddrBase + 3, pmpaddr3, pmpaddrWmask)
+  ) //++ perfCntsLoMapping
+
+  // interrupts
+
+  val mtip = WireInit(false.B)
+  val meip = WireInit(false.B)
+  val msip = WireInit(false.B)
+  BoringUtils.addSink(mtip, "mtip")
+  BoringUtils.addSink(meip, "meip")
+  BoringUtils.addSink(msip, "msip")
+  mipWire.t.m := mtip
+  mipWire.e.m := meip
+  mipWire.s.m := msip
+
+  val priv_mode = RegInit(Priv.m) // 当前特权模式
+
+  // 优先使用inst0的信息
+  val exc_sel = io.memoryUnit.in.inst(0).ex.excode.asUInt.orR ||
+    !io.memoryUnit.in.inst(1).ex.excode.asUInt.orR
+  val pc        = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
+  val exc       = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
+  val valid     = io.executeUnit.in.valid(0)
+  val op        = io.executeUnit.in.inst_info(0).op
+  val fusel     = io.executeUnit.in.inst_info(0).fusel
+  val addr      = io.executeUnit.in.inst_info(0).inst(31, 20)
+  val rdata     = Wire(UInt(XLEN.W))
+  val src1      = io.executeUnit.in.src_info(0).src1_data
+  val csri      = ZeroExtend(io.executeUnit.in.inst_info(0).inst(19, 15), XLEN)
+  val exe_stall = io.ctrl.exe_stall
+  val mem_stall = io.ctrl.mem_stall
+  val wdata = LookupTree(
+    op,
+    List(
+      CSROpType.wrt  -> src1,
+      CSROpType.set  -> (rdata | src1),
+      CSROpType.clr  -> (rdata & ~src1),
+      CSROpType.wrti -> csri, //TODO: csri --> src2
+      CSROpType.seti -> (rdata | csri),
+      CSROpType.clri -> (rdata & ~csri)
+    )
+  )
+
+  io.executeUnit.out.trap_ill := false.B
+  //val satp_legal  = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
+  val wen            = (valid && op =/= CSROpType.jmp) //&& (addr =/= Satp.U || satp_legal)
+  val illegal_mode   = priv_mode < addr(9, 8)
+  val csr_ren        = (op === CSROpType.set || op === CSROpType.seti) && src1 === 0.U
+  val illegal_write  = wen && (addr(11, 10) === "b11".U) && !csr_ren
+  val illegal_access = illegal_mode || illegal_write
+
+  MaskedRegMap.generate(mapping, addr, rdata, wen && !illegal_access, wdata)
+  val illegal_addr = MaskedRegMap.isIllegalAddr(mapping, addr)
+  // Fix Mip/Sip write
+  val fixMapping = Map(
+    MaskedRegMap(Mip, mipReg.asUInt, mipFixMask)
+    // MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) TODO
+  )
+  val rdataDummy = Wire(UInt(XLEN.W))
+  MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata)
+
+  // CSR inst decode
+  val ret      = Wire(Bool())
+  val isEbreak = addr === privEbreak && op === CSROpType.jmp
+  val isEcall  = addr === privEcall && op === CSROpType.jmp
+  val isMret   = addr === privMret && op === CSROpType.jmp
+  val isSret   = addr === privSret && op === CSROpType.jmp
+  val isUret   = addr === privUret && op === CSROpType.jmp
+  ret := isMret || isSret || isUret
+
+  val csrExceptionVec = Wire(Vec(16, Bool()))
+  csrExceptionVec.map(_         := false.B)
+  csrExceptionVec(illegalInstr) := (illegal_addr || illegal_access) && wen
+
 }
diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
index 1f93143..6f76524 100644
--- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
@@ -78,11 +78,10 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     io.inst(i).ex.out                             := io.inst(i).ex.in
     io.inst(i).ex.out.excode(loadAddrMisaligned)  := store_inst && !addr_aligned(i)
     io.inst(i).ex.out.excode(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
-    io.inst(i).ex.out.flush_req                   := io.inst(i).ex.in.flush_req || io.inst(i).ex.out.excode.asUInt.orR
   }
   io.inst(0).mem_sel := (LSUOpType.isStore(io.inst(0).inst_info.op) || LSUOpType.isLoad(io.inst(0).inst_info.op)) &&
-    !io.inst(0).ex.out.flush_req
+    !io.inst(0).ex.out.excode.asUInt.orR
   io.inst(1).mem_sel := (LSUOpType.isStore(io.inst(1).inst_info.op) || LSUOpType.isLoad(io.inst(1).inst_info.op)) &&
-    !io.inst(0).ex.out.flush_req && !io.inst(1).ex.out.flush_req
+    !io.inst(0).ex.out.excode.asUInt.orR && !io.inst(1).ex.out.excode.asUInt.orR
 
 }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index 6b62330..5ddf218 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -6,7 +6,7 @@ import cpu.CpuConfig
 import cpu.defines._
 import cpu.defines.Const._
 import cpu.pipeline.decoder.RegWrite
-import cpu.pipeline.memory.{CsrInfo, ExecuteUnitMemoryUnit}
+import cpu.pipeline.memory.ExecuteUnitMemoryUnit
 import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
 
 class ExecuteUnit(implicit val config: CpuConfig) extends Module {
@@ -45,7 +45,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
   io.csr.in.inst_info(0) := Mux(
-    !io.executeStage.inst0.ex.flush_req,
+    !io.executeStage.inst0.ex.excode.asUInt.orR,
     io.executeStage.inst0.inst_info,
     0.U.asTypeOf(new InstInfo())
   )
@@ -115,7 +115,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     accessMemCtrl.inst(0).ex.out,
     fu.inst(0).ex.out
   )
-  io.memoryStage.inst0.csr := io.csr.out.debug
 
   io.memoryStage.inst1.pc            := io.executeStage.inst1.pc
   io.memoryStage.inst1.inst_info     := io.executeStage.inst1.inst_info
diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index 7c671d0..bce97d5 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -54,7 +54,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
     // alu(i).io.div.result        := div.result
     alu(i).io.csr_rdata         := io.csr_rdata(i)
     io.inst(i).ex.out           := io.inst(i).ex.in
-    io.inst(i).ex.out.flush_req := io.inst(i).ex.in.flush_req
     io.inst(i).ex.out.excode    := io.inst(i).ex.in.excode
   }
 
diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
index 47118d7..6410c0a 100644
--- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
+++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
@@ -41,8 +41,9 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
   val mem_wdata = io.memoryUnit.in.mem_wdata
   val op        = io.memoryUnit.in.inst_info.op
   io.dataMemory.out.en := io.memoryUnit.in.mem_en &&
-    (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).flush_req ||
-      io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).flush_req && !io.memoryUnit.in.ex(1).flush_req)
+    (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).excode.asUInt.orR ||
+      io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).excode.asUInt.orR &&
+        !io.memoryUnit.in.ex(1).excode.asUInt.orR)
   io.dataMemory.out.addr := mem_addr
   val rdata = LookupTree(
     mem_addr(2, 0),
diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala
index bfc72b0..9b48b6f 100644
--- a/chisel/playground/src/pipeline/memory/MemoryStage.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala
@@ -6,12 +6,6 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class CsrInfo extends Bundle {
-  val csr_count  = UInt(DATA_WID.W)
-  val csr_random = UInt(DATA_WID.W)
-  val csr_cause  = UInt(DATA_WID.W)
-}
-
 class ExeMemInst1 extends Bundle {
   val pc        = UInt(PC_WID.W)
   val inst_info = new InstInfo()
@@ -20,7 +14,6 @@ class ExeMemInst1 extends Bundle {
 }
 
 class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
-  val csr = new CsrInfo()
   val mem = new Bundle {
     val en        = Bool()
     val ren       = Bool()
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index a8e1de6..fd9cdcb 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -62,9 +62,6 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   io.writeBackStage.inst0.ex        := io.memoryStage.inst0.ex
   io.writeBackStage.inst0.ex.excode := io.memoryStage.inst0.ex.excode
 
-  io.writeBackStage.inst0.ex.flush_req := io.memoryStage.inst0.ex.flush_req || io.writeBackStage.inst0.ex.excode.asUInt.orR
-  io.writeBackStage.inst0.csr          := io.memoryStage.inst0.csr
-
   io.writeBackStage.inst1.pc        := io.memoryStage.inst1.pc
   io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
   io.writeBackStage.inst1.rd_info.wdata := Mux(
@@ -75,8 +72,6 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   io.writeBackStage.inst1.ex        := io.memoryStage.inst1.ex
   io.writeBackStage.inst1.ex.excode := io.memoryStage.inst1.ex.excode
 
-  io.writeBackStage.inst1.ex.flush_req := io.memoryStage.inst1.ex.flush_req || io.writeBackStage.inst1.ex.excode.asUInt.orR
-
   io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc
   io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex
   io.csr.in.inst(1).pc := io.writeBackStage.inst1.pc
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
index 366b59f..1e95849 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
@@ -5,21 +5,17 @@ import chisel3.util._
 import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
-import cpu.pipeline.memory.CsrInfo
 
-class MemWbInst1 extends Bundle {
+class MemWbInst extends Bundle {
   val pc        = UInt(PC_WID.W)
   val inst_info = new InstInfo()
   val rd_info   = new RdInfo()
   val ex        = new ExceptionInfo()
 }
-class MemWbInst0 extends MemWbInst1 {
-  val csr = new CsrInfo()
-}
 
 class MemoryUnitWriteBackUnit extends Bundle {
-  val inst0 = new MemWbInst0()
-  val inst1 = new MemWbInst1()
+  val inst0 = new MemWbInst()
+  val inst1 = new MemWbInst()
 }
 class WriteBackStage(implicit val config: CpuConfig) extends Module {
   val io = IO(new Bundle {
@@ -30,12 +26,12 @@ class WriteBackStage(implicit val config: CpuConfig) extends Module {
     val memoryUnit    = Input(new MemoryUnitWriteBackUnit())
     val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
   })
-  val inst0 = RegInit(0.U.asTypeOf(new MemWbInst0()))
-  val inst1 = RegInit(0.U.asTypeOf(new MemWbInst1()))
+  val inst0 = RegInit(0.U.asTypeOf(new MemWbInst()))
+  val inst1 = RegInit(0.U.asTypeOf(new MemWbInst()))
 
   when(io.ctrl.clear(0)) {
-    inst0 := 0.U.asTypeOf(new MemWbInst0())
-    inst1 := 0.U.asTypeOf(new MemWbInst1())
+    inst0 := 0.U.asTypeOf(new MemWbInst())
+    inst1 := 0.U.asTypeOf(new MemWbInst())
   }.elsewhen(io.ctrl.allow_to_go) {
     inst0 := io.memoryUnit.inst0
     inst1 := io.memoryUnit.inst1
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 0325d90..8facc00 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -15,13 +15,14 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
     val debug          = new DEBUG()
   })
 
-  io.regfile(0)
-    .wen := io.writeBackStage.inst0.inst_info.reg_wen && io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.flush_req
+  io.regfile(0).wen := io.writeBackStage.inst0.inst_info.reg_wen &&
+    io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.excode.asUInt.orR
   io.regfile(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
   io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata
 
   io.regfile(1).wen :=
-    io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.flush_req && !io.writeBackStage.inst1.ex.flush_req
+    io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go &&
+      !io.writeBackStage.inst0.ex.excode.asUInt.orR && !io.writeBackStage.inst1.ex.excode.asUInt.orR
   io.regfile(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
   io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata
 
@@ -45,22 +46,22 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
     io.debug.wb_pc := Mux(
       clock.asBool,
       io.writeBackStage.inst0.pc,
-      Mux(io.writeBackStage.inst0.ex.flush_req, 0.U, io.writeBackStage.inst1.pc),
+      Mux(io.writeBackStage.inst0.ex.excode.asUInt.orR, 0.U, io.writeBackStage.inst1.pc)
     )
     io.debug.wb_rf_wen := Mux(
       clock.asBool,
       Fill(4, io.regfile(0).wen),
-      Fill(4, io.regfile(1).wen),
+      Fill(4, io.regfile(1).wen)
     )
     io.debug.wb_rf_wnum := Mux(
       clock.asBool,
       io.regfile(0).waddr,
-      io.regfile(1).waddr,
+      io.regfile(1).waddr
     )
     io.debug.wb_rf_wdata := Mux(
       clock.asBool,
       io.regfile(0).wdata,
-      io.regfile(1).wdata,
+      io.regfile(1).wdata
     )
   }
 }