fix: 例外判断缺少了int

chisel/playground/src/cache/ICache.scala

@@ -18,7 +18,6 @@ class ICache(implicit config: CpuConfig) extends Module {
   val status                                = RegInit(s_idle)
 
   val read_next_addr = (status === s_idle || status === s_save)
-  val addr_err       = io.cpu.addr(read_next_addr)(63, 32).orR
   val pc             = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))
 
   // default
@@ -47,7 +46,9 @@ class ICache(implicit config: CpuConfig) extends Module {
     io.cpu.inst(i)       := saved(i).inst
     io.cpu.inst_valid(i) := saved(i).valid || acc_err
   })
-  io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR
+
+  val addr_err = io.cpu.addr(read_next_addr)(63, 32).orR
+  io.cpu.addr_err := addr_err
 
   io.cpu.icache_stall := Mux(status === s_idle, io.cpu.req, status =/= s_save)
 

chisel/playground/src/pipeline/execute/Csr.scala

@@ -89,6 +89,19 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器
   val tdata1  = RegInit(0.U(XLEN.W)) // 跟踪寄存器数据1寄存器
 
+  // 仅供调试使用
+  val satp = RegInit(UInt(XLEN.W), 0.U)
+
+  val pmpcfg0      = RegInit(UInt(XLEN.W), 0.U)
+  val pmpcfg1      = RegInit(UInt(XLEN.W), 0.U)
+  val pmpcfg2      = RegInit(UInt(XLEN.W), 0.U)
+  val pmpcfg3      = RegInit(UInt(XLEN.W), 0.U)
+  val pmpaddr0     = RegInit(UInt(XLEN.W), 0.U)
+  val pmpaddr1     = RegInit(UInt(XLEN.W), 0.U)
+  val pmpaddr2     = RegInit(UInt(XLEN.W), 0.U)
+  val pmpaddr3     = RegInit(UInt(XLEN.W), 0.U)
+  val pmpaddrWmask = "h3fffffff".U(64.W) // 32bit physical address
+
   // Side Effect
   def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
     val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
@@ -133,9 +146,8 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     // MaskedRegMap(Scause, scause),
     // MaskedRegMap(Stval, stval),
     // MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
-    // // Supervisor Protection and Translation
+    // Supervisor Protection and Translation
-    // MaskedRegMap(Satp, satp),
+    MaskedRegMap(Satp, satp),
-
     // Machine Information Registers
     MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable),
     MaskedRegMap(Marchid, marchid, 0.U, MaskedRegMap.Unwritable),
@@ -156,7 +168,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     MaskedRegMap(Mcause, mcause),
     MaskedRegMap(Mtval, mtval),
     MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable)
-    // // Machine Memory Protection TODO
+    // Machine Memory Protection
     // MaskedRegMap(Pmpcfg0, pmpcfg0),
     // MaskedRegMap(Pmpcfg1, pmpcfg1),
     // MaskedRegMap(Pmpcfg2, pmpcfg2),
@@ -187,8 +199,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   io.decoderUnit.interrupt := mie(11, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
 
   // 优先使用inst0的信息
-  val exc_sel = io.memoryUnit.in.inst(0).ex.exception.asUInt.orR ||
+  val exc_sel =
-    !io.memoryUnit.in.inst(1).ex.exception.asUInt.orR
+    (io.memoryUnit.in.inst(0).ex.exception.asUInt.orR || io.memoryUnit.in.inst(0).ex.interrupt.asUInt.orR) ||
+      !(io.memoryUnit.in.inst(1).ex.exception.asUInt.orR || io.memoryUnit.in.inst(1).ex.interrupt.asUInt.orR)
   val pc        = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
   val exc       = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
   val valid     = io.executeUnit.in.valid
@@ -212,11 +225,11 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     )
   )
 
-  //val satp_legal  = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
+  val satp_legal     = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
-  val wen            = (valid && op =/= CSROpType.jmp) //&& (addr =/= Satp.U || satp_legal)
+  val wen            = (valid && op =/= CSROpType.jmp) && (addr =/= Satp.U || satp_legal)
+  val ren            = (op === CSROpType.set || op === CSROpType.seti) && src1 === 0.U
   val illegal_mode   = priv_mode < addr(9, 8)
-  val csr_ren        = (op === CSROpType.set || op === CSROpType.seti) && src1 === 0.U
+  val illegal_write  = wen && (addr(11, 10) === "b11".U) && !ren
-  val illegal_write  = wen && (addr(11, 10) === "b11".U) && !csr_ren
   val illegal_access = illegal_mode || illegal_write
 
   MaskedRegMap.generate(mapping, addr, rdata, wen && !illegal_access, wdata)

chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala

@@ -80,8 +80,11 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
   }
   io.inst(0).mem_sel := (io.inst(0).inst_info.fusel === FuType.lsu) &&
-    !io.inst(0).ex.out.exception.asUInt.orR && io.inst(0).inst_info.valid
+    !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
+    io.inst(0).inst_info.valid
   io.inst(1).mem_sel := (io.inst(1).inst_info.fusel === FuType.lsu) &&
-    !io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR && io.inst(1).inst_info.valid
+    !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
+    !(io.inst(1).ex.out.exception.asUInt.orR || io.inst(1).ex.out.interrupt.asUInt.orR) &&
+    io.inst(1).inst_info.valid
 
 }

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -46,9 +46,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
   val csr_sel0 = valid(0) && io.executeStage.inst0.inst_info.fusel === FuType.csr &&
-    !io.executeStage.inst0.ex.exception.asUInt.orR
+    !(io.executeStage.inst0.ex.exception.asUInt.orR|| io.executeStage.inst0.ex.interrupt.asUInt.orR)
   val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
-    !io.executeStage.inst1.ex.exception.asUInt.orR
+    !(io.executeStage.inst1.ex.exception.asUInt.orR|| io.executeStage.inst1.ex.interrupt.asUInt.orR)
   io.csr.in.valid := csr_sel0 || csr_sel1
   io.csr.in.inst_info := Mux(
     csr_sel0 && !csr_sel1,

chisel/playground/src/pipeline/memory/DataMemoryAccess.scala

@@ -42,9 +42,11 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
   val mem_wdata = io.memoryUnit.in.mem_wdata
   val op        = io.memoryUnit.in.inst_info.op
   io.dataMemory.out.en := io.memoryUnit.in.mem_en &&
-    (io.memoryUnit.in.mem_sel(0) && !io.memoryUnit.in.ex(0).exception.asUInt.orR ||
+    (io.memoryUnit.in.mem_sel(0) &&
-      io.memoryUnit.in.mem_sel(1) && !io.memoryUnit.in.ex(0).exception.asUInt.orR &&
+      !(io.memoryUnit.in.ex(0).exception.asUInt.orR || io.memoryUnit.in.ex(0).interrupt.asUInt.orR) ||
-        !io.memoryUnit.in.ex(1).exception.asUInt.orR)
+      io.memoryUnit.in.mem_sel(1) &&
+        !(io.memoryUnit.in.ex(0).exception.asUInt.orR || io.memoryUnit.in.ex(0).interrupt.asUInt.orR) &&
+        !(io.memoryUnit.in.ex(1).exception.asUInt.orR || io.memoryUnit.in.ex(1).interrupt.asUInt.orR))
   io.dataMemory.out.addr := mem_addr
   val rdata = LookupTree(
     mem_addr(2, 0),

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -67,7 +67,8 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
   io.writeBackStage.inst1.ex                        := io.memoryStage.inst1.ex
   io.writeBackStage.inst1.ex.exception              := io.memoryStage.inst1.ex.exception
-  io.writeBackStage.inst1.commit                    := io.memoryStage.inst1.inst_info.valid
+  io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid &&
+    !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
 
   io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc
   io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex

chisel/playground/src/pipeline/writeback/WriteBackUnit.scala

@@ -16,13 +16,15 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
   })
 
   io.regfile(0).wen := io.writeBackStage.inst0.inst_info.reg_wen &&
-    io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.exception.asUInt.orR
+    io.ctrl.allow_to_go &&
+    !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
   io.regfile(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
   io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
 
   io.regfile(1).wen :=
     io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go &&
-      !io.writeBackStage.inst0.ex.exception.asUInt.orR && !io.writeBackStage.inst1.ex.exception.asUInt.orR
+      !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR) &&
+      !(io.writeBackStage.inst1.ex.exception.asUInt.orR || io.writeBackStage.inst1.ex.interrupt.asUInt.orR)
   io.regfile(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
   io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
 
@@ -46,7 +48,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
     io.debug.wb_pc := Mux(
       clock.asBool,
       io.writeBackStage.inst0.pc,
-      Mux(io.writeBackStage.inst0.ex.exception.asUInt.orR, 0.U, io.writeBackStage.inst1.pc)
+      Mux(
+        io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR,
+        0.U,
+        io.writeBackStage.inst1.pc
+      )
     )
     io.debug.wb_rf_wen := Mux(
       clock.asBool,