From 5101abc727f661fd359ba710e6cef45c8e20ec4b Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Wed, 13 Dec 2023 13:00:35 +0800
Subject: [PATCH] =?UTF-8?q?refactor:=20=E5=88=A0=E5=8E=BB=E6=97=A0?=
 =?UTF-8?q?=E7=94=A8=E4=BF=A1=E5=8F=B7?=
MIME-Version: 1.0
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---
 chisel/playground/src/ctrl/Ctrl.scala         |  2 +-
 .../src/pipeline/decoder/DecoderUnit.scala    |  6 +++---
 .../playground/src/pipeline/execute/ALU.scala | 20 +++----------------
 3 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/chisel/playground/src/ctrl/Ctrl.scala b/chisel/playground/src/ctrl/Ctrl.scala
index ed83087..d6b7eed 100644
--- a/chisel/playground/src/ctrl/Ctrl.scala
+++ b/chisel/playground/src/ctrl/Ctrl.scala
@@ -23,7 +23,7 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
     (io.decoderUnit.inst0.src1.ren && io.decoderUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr ||
       io.decoderUnit.inst0.src2.ren && io.decoderUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr)
   val lw_stall = inst0_lw_stall || inst1_lw_stall
-  // TODO: 这里的stall信号可能不对
+  // TODO: 这里的stall信号可以改进，尝试让前后端完全解耦
   val longest_stall =
     io.executeUnit.fu_stall || io.cacheCtrl.iCache_stall || io.memoryUnit.mem_stall
 
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index 80fab7d..5db2feb 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -83,10 +83,10 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.regfile(1).src1.raddr := info(1).reg1_raddr
   io.regfile(1).src2.raddr := info(1).reg2_raddr
   forwardCtrl.in.forward   := io.forward
-  forwardCtrl.in.regfile   := io.regfile // TODO:这里的连接可能有问题
+  forwardCtrl.in.regfile   := io.regfile
   jumpCtrl.in.info         := info(0)
   jumpCtrl.in.forward      := io.forward
-  jumpCtrl.in.pc           := io.instFifo.inst(0).pc
+  jumpCtrl.in.pc           := pc(0)
   jumpCtrl.in.src_info     := io.executeStage.inst0.src_info
 
   val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch
@@ -95,7 +95,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target)
 
   io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
-  io.bpu.pc                  := io.instFifo.inst(0).pc
+  io.bpu.pc                  := pc(0)
   io.bpu.info                := info(0)
   io.bpu.pht_index           := io.instFifo.inst(0).pht_index
 
diff --git a/chisel/playground/src/pipeline/execute/ALU.scala b/chisel/playground/src/pipeline/execute/ALU.scala
index 068aba4..4492771 100644
--- a/chisel/playground/src/pipeline/execute/ALU.scala
+++ b/chisel/playground/src/pipeline/execute/ALU.scala
@@ -5,25 +5,11 @@ import chisel3.util._
 import cpu.defines._
 import cpu.defines.Const._
 
-class DivSignal extends Bundle {
-  val ready  = Input(Bool())
-  val result = Input(UInt(64.W))
-
-  val en     = Output(Bool())
-  val signed = Output(Bool())
-}
-class MultSignal extends Bundle {
-  val ready  = Input(Bool())
-  val result = Input(UInt(64.W))
-
-  val en     = Output(Bool())
-  val signed = Output(Bool())
-}
 class Alu extends Module {
   val io = IO(new Bundle {
-    val info = Input(new InstInfo())
-    val src_info  = Input(new SrcInfo())
-    val result    = Output(UInt(DATA_WID.W))
+    val info     = Input(new InstInfo())
+    val src_info = Input(new SrcInfo())
+    val result   = Output(UInt(DATA_WID.W))
   })
   val op     = io.info.op
   val src1   = io.src_info.src1_data