diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index a7497ca..91c196f 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -30,27 +30,5 @@ class Core extends Module { fetchUnit.instSram <> io.instSram fetchUnit.decodeStage <> decodeStage.fetchUnit - // 译码级缓存 - decodeStage.decodeUnit <> decodeUnit.decodeStage - // 译码单元 - decodeUnit.regfile <> regfile.read - decodeUnit.executeStage <> executeStage.decodeUnit - - // 执行级缓存 - executeStage.executeUnit <> executeUnit.executeStage - executeUnit.dataSram <> io.dataSram - // 执行单元 - executeUnit.memoryStage <> memoryStage.executeUnit - // 访存级缓存 - memoryStage.memoryUnit <> memoryUnit.memoryStage - // 访存单元 - memoryUnit.writeBackStage <> writeBackStage.memoryUnit - - // 写回级缓存 - writeBackStage.memoryUnit <> memoryUnit.writeBackStage - // 写回单元 - writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit - writeBackUnit.regfile <> regfile.write - writeBackUnit.debug <> io.debug - + // TODO: 完成Core模块的逻辑 } diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala index 91039e3..980615d 100644 --- a/chisel/playground/src/defines/isa/Instructions.scala +++ b/chisel/playground/src/defines/isa/Instructions.scala @@ -22,28 +22,11 @@ object FuType { } object FuOpType { - def apply() = UInt(6.W) + def apply() = UInt(5.W) } // ALU object ALUOpType { - def add = "b100000".U - def sll = "b000001".U - def slt = "b000010".U - def sltu = "b000011".U - def xor = "b000100".U - def srl = "b000101".U - def or = "b000110".U - def and = "b000111".U - def sub = "b001000".U - def sra = "b001101".U - - def addw = "b110000".U - def subw = "b011000".U - def sllw = "b010001".U - def srlw = "b010101".U - def sraw = "b011101".U - - def isWordOp(func: UInt) = func(4) - def isAdd(func: UInt) = func(5) + def add = "b00000".U + // TODO: 定义更多的ALU操作类型 } diff --git a/chisel/playground/src/defines/isa/RVI.scala b/chisel/playground/src/defines/isa/RVI.scala index 34459a2..31c0741 100644 --- a/chisel/playground/src/defines/isa/RVI.scala +++ b/chisel/playground/src/defines/isa/RVI.scala @@ -33,26 +33,7 @@ object RV32I_ALUInstr extends HasInstrType with CoreParameter { val table = Array( ADDI -> List(InstrI, FuType.alu, ALUOpType.add), - SLLI -> List(InstrI, FuType.alu, ALUOpType.sll), - SLTI -> List(InstrI, FuType.alu, ALUOpType.slt), - SLTIU -> List(InstrI, FuType.alu, ALUOpType.sltu), - XORI -> List(InstrI, FuType.alu, ALUOpType.xor), - SRLI -> List(InstrI, FuType.alu, ALUOpType.srl), - ORI -> List(InstrI, FuType.alu, ALUOpType.or), - ANDI -> List(InstrI, FuType.alu, ALUOpType.and), - SRAI -> List(InstrI, FuType.alu, ALUOpType.sra), - ADD -> List(InstrR, FuType.alu, ALUOpType.add), - SLL -> List(InstrR, FuType.alu, ALUOpType.sll), - SLT -> List(InstrR, FuType.alu, ALUOpType.slt), - SLTU -> List(InstrR, FuType.alu, ALUOpType.sltu), - XOR -> List(InstrR, FuType.alu, ALUOpType.xor), - SRL -> List(InstrR, FuType.alu, ALUOpType.srl), - OR -> List(InstrR, FuType.alu, ALUOpType.or), - AND -> List(InstrR, FuType.alu, ALUOpType.and), - SUB -> List(InstrR, FuType.alu, ALUOpType.sub), - SRA -> List(InstrR, FuType.alu, ALUOpType.sra), - AUIPC -> List(InstrU, FuType.alu, ALUOpType.add), - LUI -> List(InstrU, FuType.alu, ALUOpType.add) + // TODO: 完成其他指令的解析 ) } @@ -68,15 +49,7 @@ object RV64IInstr extends HasInstrType { def SUBW = BitPat("b0100000_?????_?????_000_?????_0111011") val table = Array( - ADDIW -> List(InstrI, FuType.alu, ALUOpType.addw), - SLLIW -> List(InstrI, FuType.alu, ALUOpType.sllw), - SRLIW -> List(InstrI, FuType.alu, ALUOpType.srlw), - SRAIW -> List(InstrI, FuType.alu, ALUOpType.sraw), - SLLW -> List(InstrR, FuType.alu, ALUOpType.sllw), - SRLW -> List(InstrR, FuType.alu, ALUOpType.srlw), - SRAW -> List(InstrR, FuType.alu, ALUOpType.sraw), - ADDW -> List(InstrR, FuType.alu, ALUOpType.addw), - SUBW -> List(InstrR, FuType.alu, ALUOpType.subw) + // TODO: 完成RV64I指令集的解析 ) } diff --git a/chisel/playground/src/pipeline/decode/ARegfile.scala b/chisel/playground/src/pipeline/decode/ARegfile.scala index 59518d5..acbb27a 100644 --- a/chisel/playground/src/pipeline/decode/ARegfile.scala +++ b/chisel/playground/src/pipeline/decode/ARegfile.scala @@ -32,21 +32,10 @@ class ARegFile extends Module { val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W)))) // 写寄存器堆 - when(io.write.wen && io.write.waddr =/= 0.U) { - regs(io.write.waddr) := io.write.wdata - } + // TODO:完成写寄存器堆逻辑 + // 注意：0号寄存器恒为0 // 读寄存器堆 - // src1 - when(io.read.src1.raddr === 0.U) { - io.read.src1.rdata := 0.U - }.otherwise { - io.read.src1.rdata := regs(io.read.src1.raddr) - } - // src2 - when(io.read.src2.raddr === 0.U) { - io.read.src2.rdata := 0.U - }.otherwise { - io.read.src2.rdata := regs(io.read.src2.raddr) - } + // TODO:完成读寄存器堆逻辑 + // 注意：0号寄存器恒为0 } diff --git a/chisel/playground/src/pipeline/decode/DecodeUnit.scala b/chisel/playground/src/pipeline/decode/DecodeUnit.scala index 3332bc9..52c4e96 100644 --- a/chisel/playground/src/pipeline/decode/DecodeUnit.scala +++ b/chisel/playground/src/pipeline/decode/DecodeUnit.scala @@ -23,12 +23,14 @@ class DecodeUnit extends Module { info := decoder.out.info info.valid := io.decodeStage.data.valid - io.regfile.src1.raddr := info.src1_raddr - io.regfile.src2.raddr := info.src2_raddr + // TODO:完成寄存器堆的读取 + // io.regfile.src1.raddr := + // io.regfile.src2.raddr := - io.executeStage.data.pc := pc - io.executeStage.data.info := info - io.executeStage.data.src_info.src1_data := io.regfile.src1.rdata - io.executeStage.data.src_info.src2_data := io.regfile.src2.rdata + // TODO: 完成DecodeUnit模块的逻辑 + // io.executeStage.data.pc := + // io.executeStage.data.info := + // io.executeStage.data.src_info.src1_data := + // io.executeStage.data.src_info.src2_data := } diff --git a/chisel/playground/src/pipeline/decode/Decoder.scala b/chisel/playground/src/pipeline/decode/Decoder.scala index cd88940..834a6ba 100644 --- a/chisel/playground/src/pipeline/decode/Decoder.scala +++ b/chisel/playground/src/pipeline/decode/Decoder.scala @@ -16,17 +16,5 @@ class Decoder extends Module with HasInstrType { val info = new Info() }) }) - - val inst = io.in.inst - val instrType :: fuType :: fuOpType :: Nil = - ListLookup(inst, Instructions.DecodeDefault, Instructions.DecodeTable) - - val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7)) - - io.out.info.valid := false.B - io.out.info.src1_raddr := rs - io.out.info.src2_raddr := rt - io.out.info.op := fuOpType - io.out.info.reg_wen := isRegWen(instrType) - io.out.info.reg_waddr := Mux(isRegWen(instrType), rd, 0.U) + // TODO: 完成Decoder模块的逻辑 } diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala index a7b6336..ab1c700 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala @@ -24,7 +24,5 @@ class ExecuteStage extends Module { val data = RegInit(0.U.asTypeOf(new IdExeData())) - data := io.decodeUnit.data - - io.executeUnit.data := data + // TODO: 完成ExecuteStage模块的逻辑 } diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 00736a5..5ca9a74 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -21,8 +21,9 @@ class ExecuteUnit extends Module { io.dataSram <> fu.dataSram - io.memoryStage.data.pc := io.executeStage.data.pc - io.memoryStage.data.info := io.executeStage.data.info - io.memoryStage.data.src_info := io.executeStage.data.src_info - io.memoryStage.data.rd_info := fu.data.rd_info + // TODO: 完成ExecuteUnit模块的逻辑 + // io.memoryStage.data.pc := + // io.memoryStage.data.info := + // io.memoryStage.data.src_info := + // io.memoryStage.data.rd_info := } diff --git a/chisel/playground/src/pipeline/execute/fu/Alu.scala b/chisel/playground/src/pipeline/execute/fu/Alu.scala index 171f6d7..940731c 100644 --- a/chisel/playground/src/pipeline/execute/fu/Alu.scala +++ b/chisel/playground/src/pipeline/execute/fu/Alu.scala @@ -11,33 +11,5 @@ class Alu extends Module { val src_info = Input(new SrcInfo()) val result = Output(UInt(XLEN.W)) }) - val op = io.info.op - val src1 = io.src_info.src1_data - val src2 = io.src_info.src2_data - val is_sub = !ALUOpType.isAdd(op) - val sum = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub - val xor = src1 ^ src2 - val sltu = !sum(XLEN) - val slt = xor(XLEN - 1) ^ sltu - - val shsrc1 = MuxLookup(op, src1(XLEN - 1, 0))( - List( - ALUOpType.srlw -> ZeroExtend(src1(31, 0), XLEN), - ALUOpType.sraw -> SignedExtend(src1(31, 0), XLEN) - ) - ) - val shamt = Mux(ALUOpType.isWordOp(op), src2(4, 0), if (XLEN == 64) src2(5, 0) else src2(4, 0)) - val res = MuxLookup(op(3, 0), sum)( - List( - ALUOpType.sll -> ((shsrc1 << shamt)(XLEN - 1, 0)), - ALUOpType.slt -> ZeroExtend(slt, XLEN), - ALUOpType.sltu -> ZeroExtend(sltu, XLEN), - ALUOpType.xor -> xor, - ALUOpType.srl -> (shsrc1 >> shamt), - ALUOpType.or -> (src1 | src2), - ALUOpType.and -> (src1 & src2), - ALUOpType.sra -> ((shsrc1.asSInt >> shamt).asUInt) - ) - ) - io.result := Mux(ALUOpType.isWordOp(op), SignedExtend(res(31, 0), 64), res) + // TODO: 完成ALU模块的逻辑 } diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala index 468147f..56ca780 100644 --- a/chisel/playground/src/pipeline/memory/MemoryStage.scala +++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala @@ -25,7 +25,5 @@ class MemoryStage extends Module { val data = RegInit(0.U.asTypeOf(new ExeMemData())) - data := io.executeUnit.data - - io.memoryUnit.data := data + // TODO: 完成MemoryStage模块的逻辑 } diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala index ec5a3a6..a6ef612 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala @@ -22,7 +22,6 @@ class WriteBackStage extends Module { }) val data = RegInit(0.U.asTypeOf(new MemWbData())) - data := io.memoryUnit.data - - io.writeBackUnit.data := data + + // TODO: 完成WriteBackStage模块的逻辑 } diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala index 8995aec..0bc3c2a 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala @@ -13,15 +13,5 @@ class WriteBackUnit extends Module { val debug = new DEBUG() }) - io.regfile.wen := - io.writeBackStage.data.info.valid && - io.writeBackStage.data.info.reg_wen - - io.regfile.waddr := io.writeBackStage.data.info.reg_waddr - io.regfile.wdata := io.writeBackStage.data.rd_info.wdata - - io.debug.pc := io.writeBackStage.data.pc - io.debug.commit := io.writeBackStage.data.info.valid - io.debug.rf_wnum := io.regfile.waddr - io.debug.rf_wdata := io.regfile.wdata + // TODO: 完成WriteBackUnit模块的逻辑 }