fix(icache): 修复之前icache遗留的问题
This commit is contained in:
Liphen
parent
f4e0e1b5be
commit
442f51d5a4
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@ -28,23 +28,22 @@ case class BranchPredictorConfig(
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val phtDepth: Int = 6)
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case class CacheConfig(
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nway: Int = 2, // 路数
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nbank: Int = 8, // 每个项目中的bank数
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nindex: Int, // 每路的项目数
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bankWidth: Int // 每个bank中的字节数
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nway: Int = 2, // 路数
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nbank: Int, // 每个项目中的bank数
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nindex: Int, // 每路的项目数
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bytesPerBank: Int // 每个bank中的字节数
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) {
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val config = CpuConfig()
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val indexWidth = log2Ceil(nindex) // index的位宽
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val bankIndexWidth = log2Ceil(nbank)
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val bankOffsetWidth = log2Ceil(bankWidth)
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val bankOffsetWidth = log2Ceil(bytesPerBank)
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val offsetWidth = bankIndexWidth + bankOffsetWidth // offset的位宽
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val tagWidth = 32 - indexWidth - offsetWidth // tag的位宽
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val bankWidthBits = bankWidth * 8
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val burstSize = 16
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val bitsPerBank = bytesPerBank * 8
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require(isPow2(nindex))
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require(isPow2(nway))
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require(isPow2(nbank))
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require(isPow2(bankWidth))
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require(isPow2(bytesPerBank))
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require(
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tagWidth + indexWidth + bankIndexWidth + bankOffsetWidth == 32,
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"basic request calculation"
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@ -15,9 +15,9 @@ class Cache(implicit config: CpuConfig) extends Module {
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})
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implicit val iCacheConfig =
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CacheConfig(nindex = 64, nbank = 4, bankWidth = (32 / 8) * 4) // 每个 bank 存 4 条 32 bit 指令
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CacheConfig(nindex = 64, nbank = 4, bytesPerBank = (32 / 8) * config.instFetchNum) // 每个 bank 存 2 条 32 bit 指令
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implicit val dCacheConfig =
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CacheConfig(nindex = 128, bankWidth = XLEN / 8) // 每个 bank 存 1 条 XLEN bit 数据
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CacheConfig(nindex = 128, nbank = 8, bytesPerBank = XLEN / 8) // 每个 bank 存 1 条 XLEN bit 数据
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val icache = Module(new ICache(iCacheConfig))
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val dcache = Module(new DCache(dCacheConfig))
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@ -16,12 +16,12 @@ class WriteBufferUnit extends Bundle {
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}
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class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module {
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val nway: Int = cacheConfig.nway
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val nset: Int = cacheConfig.nindex
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val nbank: Int = cacheConfig.nbank
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val bankWidthBits: Int = cacheConfig.bankWidthBits
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val tagWidth: Int = cacheConfig.tagWidth
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val burstSize: Int = cacheConfig.burstSize
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val nway: Int = cacheConfig.nway
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val nindex: Int = cacheConfig.nindex
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val nbank: Int = cacheConfig.nbank
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val bitsPerBank: Int = cacheConfig.bitsPerBank
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val tagWidth: Int = cacheConfig.tagWidth
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val burstSize: Int = 16
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val io = IO(new Bundle {
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val cpu = Flipped(new Cache_DCache())
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@ -37,9 +37,9 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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io.cpu.tlb.dcache_is_idle := state === s_idle
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// * valid dirty * //
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val valid = RegInit(VecInit(Seq.fill(nset)(VecInit(Seq.fill(nway)(false.B)))))
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val dirty = RegInit(VecInit(Seq.fill(nset)(VecInit(Seq.fill(nway)(false.B)))))
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val lru = RegInit(VecInit(Seq.fill(nset)(0.U(1.W))))
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val valid = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B)))))
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val dirty = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B)))))
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val lru = RegInit(VecInit(Seq.fill(nindex)(0.U(1.W))))
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val write_fifo = Module(new Queue(new WriteBufferUnit(), 4))
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@ -115,7 +115,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// bank tagv ram
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for { i <- 0 until nway } {
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val bank_ram = Module(new SimpleDualPortRam(nset * nbank, bankWidthBits, byteAddressable = true))
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val bank_ram = Module(new SimpleDualPortRam(nindex * nbank, bitsPerBank, byteAddressable = true))
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bank_ram.io.ren := true.B
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bank_ram.io.raddr := data_raddr
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data(i) := bank_ram.io.rdata
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@ -125,7 +125,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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bank_ram.io.wdata := data_wdata
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bank_ram.io.wstrb := data_wstrb(i)
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val tag_ram = Module(new LUTRam(nset, tagWidth))
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val tag_ram = Module(new LUTRam(nindex, tagWidth))
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tag_ram.io.raddr := tag_raddr
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tag(i) := tag_ram.io.rdata
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@ -10,35 +10,37 @@ import cpu.defines.Const._
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class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module {
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val nway: Int = cacheConfig.nway
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val nset: Int = cacheConfig.nindex
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val nindex: Int = cacheConfig.nindex
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val nbank: Int = cacheConfig.nbank
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val ninst: Int = config.instFetchNum
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val instFetchNum: Int = config.instFetchNum
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val bankOffsetWidth: Int = cacheConfig.bankOffsetWidth
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val bankWidth: Int = cacheConfig.bankWidth
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val bankIndexWidth: Int = cacheConfig.offsetWidth - bankOffsetWidth
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val bytesPerBank: Int = cacheConfig.bytesPerBank
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val tagWidth: Int = cacheConfig.tagWidth
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val indexWidth: Int = cacheConfig.indexWidth
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val offsetWidth: Int = cacheConfig.offsetWidth
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val bitsPerBank: Int = cacheConfig.bitsPerBank
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val io = IO(new Bundle {
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val cpu = Flipped(new Cache_ICache())
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val axi = new ICache_AXIInterface()
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})
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require(isPow2(ninst), "ninst must be power of 2")
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// * addr organization * //
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// ======================================
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// | tag | index |offset|
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// |31 12|11 6|5 0|
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// ======================================
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// | offset |
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// | bank index | bank offset |
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// | 5 4 | 3 2 |
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// ============================
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require(isPow2(instFetchNum), "ninst must be power of 2")
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// 整个宽度为PADDR_WID的地址
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// ==========================================================
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// | tag | index | offset |
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// | | | bank index | bank offset |
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// ==========================================================
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val bank_index = io.cpu.addr(0)(offsetWidth - 1, bankOffsetWidth)
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val bank_offset = io.cpu.addr(0)(bankOffsetWidth - 1, 2) // PC低2位必定是0
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val tlb_fill = RegInit(false.B)
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// * fsm * //
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val s_idle :: s_uncached :: s_replace :: s_save :: Nil = Enum(4)
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val state = RegInit(s_idle)
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// * nway * nset * //
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// * nway * nindex * //
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// * 128 bit for 4 inst * //
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// =========================================================
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// | valid | tag | bank 0 | bank 1 | bank 2 | bank 3 |
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@ -48,24 +50,24 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// | inst 0 | inst 1 | inst 2 | inst 3 |
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// | 32 | 32 | 32 | 32 |
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// =====================================
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val instperbank = bankWidth / 4 // 每个bank存储的指令数
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val valid = RegInit(VecInit(Seq.fill(nset * nbank)(VecInit(Seq.fill(instperbank)(false.B)))))
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require(instFetchNum == bytesPerBank / 4, "instFetchNum must equal to instperbank")
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val valid = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nbank)(false.B)))))
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val data = Wire(Vec(nway, Vec(instperbank, UInt(XLEN.W))))
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val data = Wire(Vec(nway, Vec(nbank, UInt(XLEN.W))))
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val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
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// * should choose next addr * //
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val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_save)
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val data_raddr = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, bankOffsetWidth)
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val data_wstrb = RegInit(VecInit(Seq.fill(nway)(VecInit(Seq.fill(instperbank)(0.U(4.W))))))
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val data_raddr = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
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val data_wstrb = RegInit(VecInit(Seq.fill(nway)(VecInit(Seq.fill(nbank)(false.B)))))
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val tag_raddr = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
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val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
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val tag_wdata = RegInit(0.U(tagWidth.W))
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// * lru * //
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val lru = RegInit(VecInit(Seq.fill(nset * nbank)(false.B)))
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val lru = RegInit(VecInit(Seq.fill(nindex * nbank)(false.B)))
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// * itlb * //
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when(tlb_fill) { tlb_fill := false.B }
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@ -73,64 +75,85 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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io.cpu.tlb.icache_is_save := (state === s_save)
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// * fence * //
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// fence指令时清空cache，即将所有valid位置0
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when(io.cpu.fence && !io.cpu.icache_stall && io.cpu.cpu_ready) {
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valid.map(_ := VecInit(Seq.fill(instperbank)(false.B)))
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valid := 0.U.asTypeOf(valid)
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}
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// * replace set * //
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val rset = RegInit(0.U(6.W))
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// * replace index * //
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val rindex = RegInit(0.U(indexWidth.W))
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// * virtual set * //
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val vset = io.cpu.addr(0)(indexWidth + offsetWidth - 1, offsetWidth)
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// * virtual index * //
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val vindex = io.cpu.addr(0)(indexWidth + offsetWidth - 1, offsetWidth)
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// * cache hit * //
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val tag_compare_valid = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.tag && valid(vset)(i)))
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val tag_compare_valid = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.tag && valid(vindex)(i)))
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val cache_hit = tag_compare_valid.contains(true.B)
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val cache_hit_available = cache_hit && io.cpu.tlb.translation_ok && !io.cpu.tlb.uncached
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val sel = tag_compare_valid(1)
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val bank_offset = io.cpu.addr(0)(log2Ceil(instperbank) + 1, 2)
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val inst = VecInit(
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Seq.tabulate(instperbank)(i => Mux(i.U <= (3.U - bank_offset), data(sel)(i.U + bank_offset), 0.U))
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// 将一个 bank 中的指令分成 instFetchNum 份，每份 INST_WID bit
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val inst_in_bank = VecInit(
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Seq.tabulate(instFetchNum)(i => data(sel)(bank_index)((i + 1) * INST_WID - 1, i * INST_WID))
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)
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val inst_valid = VecInit(Seq.tabulate(instperbank)(i => cache_hit_available && i.U <= (3.U - bank_offset)))
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val saved = RegInit(VecInit(Seq.fill(instperbank)(0.U.asTypeOf(new Bundle {
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// 将 inst_in_bank 中的指令按照 bank_offset 位偏移量重新排列
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// 处理偏移导致的跨 bank 读取
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// 当offset为0时，不需要重新排列
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// 当offset为1时，此时发送到cpu的inst0应该是inst1，inst1应该无数据
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// | bank |
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// | inst 0 | inst 1 |
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// | 32 | 32 |
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val inst = VecInit(
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Seq.tabulate(instFetchNum)(i =>
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Mux(
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i.U <= ((instFetchNum - 1).U - bank_offset),
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inst_in_bank(i.U + bank_offset),
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0.U
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)
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)
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)
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val inst_valid = VecInit(
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Seq.tabulate(instFetchNum)(i => cache_hit_available && i.U <= ((instFetchNum - 1).U - bank_offset))
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)
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val saved = RegInit(VecInit(Seq.fill(instFetchNum)(0.U.asTypeOf(new Bundle {
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val inst = UInt(INST_WID.W)
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val valid = Bool()
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}))))
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val axi_cnt = Counter(cacheConfig.burstSize)
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val rlen = nbank
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val rsize = log2Ceil(bytesPerBank)
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// bank tag ram
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for { i <- 0 until nway; j <- 0 until instperbank } {
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val bank = Module(new SimpleDualPortRam(nset * nbank, INST_WID, byteAddressable = true))
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bank.io.ren := true.B
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bank.io.raddr := data_raddr
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data(i)(j) := bank.io.rdata
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for { i <- 0 until nway } {
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// 每一个条目中有nbank个bank，每个bank存储instFetchNum个指令
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val bank =
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Seq.fill(nbank)(Module(new SimpleDualPortRam(depth = nindex, width = bitsPerBank, byteAddressable = false)))
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for { j <- 0 until nbank } {
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bank(j).io.ren := true.B
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bank(j).io.raddr := data_raddr
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data(i)(j) := bank(j).io.rdata
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bank.io.wen := data_wstrb(i)(j).orR
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bank.io.waddr := Cat(rset, axi_cnt.value(log2Ceil(cacheConfig.burstSize) - 1, log2Ceil(instperbank)))
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bank.io.wdata := Mux(
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j.U === axi_cnt.value(log2Ceil(instperbank) - 1, 0),
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Mux(axi_cnt.value(0) === 0.U, io.axi.r.bits.data(31, 0), io.axi.r.bits.data(63, 32)),
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0.U
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)
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bank.io.wstrb := data_wstrb(i)(j)
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bank(j).io.wen := data_wstrb(i)(j)
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bank(j).io.waddr := rindex
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bank(j).io.wdata := io.axi.r.bits.data
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bank(j).io.wstrb := data_wstrb(i)(j)
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}
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}
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for { i <- 0 until ninst } {
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for { i <- 0 until instFetchNum } {
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io.cpu.inst_valid(i) := Mux(state === s_idle && !tlb_fill, inst_valid(i), saved(i).valid) && io.cpu.req
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io.cpu.inst(i) := Mux(state === s_idle && !tlb_fill, inst(i), saved(i).inst)
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}
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for { i <- 0 until nway } {
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val tag_bram = Module(new LUTRam(nset, tagWidth))
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val tag_bram = Module(new LUTRam(nindex, tagWidth))
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tag_bram.io.raddr := tag_raddr
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tag(i) := tag_bram.io.rdata
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tag_bram.io.wen := tag_wstrb(i)
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tag_bram.io.waddr := rset
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tag_bram.io.waddr := rindex
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tag_bram.io.wdata := tag_wdata
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}
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@ -171,28 +194,29 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}.elsewhen(io.cpu.tlb.uncached) {
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state := s_uncached
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ar.addr := io.cpu.tlb.pa
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ar.len := 0.U(log2Ceil((nbank * bankWidth) / 4).W)
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ar.size := 2.U(bankOffsetWidth.W)
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ar.len := 0.U
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ar.size := rsize.U
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arvalid := true.B
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}.elsewhen(!cache_hit) {
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state := s_replace
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ar.addr := Cat(io.cpu.tlb.pa(31, 6), 0.U(6.W))
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ar.len := 15.U(log2Ceil((nbank * bankWidth) / 4).W)
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ar.size := 2.U(bankOffsetWidth.W)
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state := s_replace
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// 取指时按bank块取指
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ar.addr := Cat(io.cpu.tlb.pa(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
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ar.len := (rlen - 1).U
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ar.size := rsize.U
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arvalid := true.B
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rset := vset
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(0 until instperbank).foreach(i => data_wstrb(lru(vset))(i) := Mux(i.U === 0.U, 0xf.U, 0x0.U))
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tag_wstrb(lru(vset)) := true.B
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tag_wdata := io.cpu.tlb.tag
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valid(vset)(lru(vset)) := true.B
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axi_cnt.reset()
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rindex := vindex
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data_wstrb(lru(vindex)).map(_ := false.B)
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data_wstrb(lru(vindex))(0) := true.B // 从第一个bank开始写入
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tag_wstrb(lru(vindex)) := true.B
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tag_wdata := io.cpu.tlb.tag
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valid(vindex)(lru(vindex)) := true.B
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}.elsewhen(!io.cpu.icache_stall) {
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lru(vset) := ~sel
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lru(vindex) := ~sel
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when(!io.cpu.cpu_ready) {
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state := s_save
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(1 until instperbank).foreach(i => saved(i).inst := data(sel)(i))
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(0 until instperbank).foreach(i => saved(i).valid := inst_valid(i))
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(1 until instFetchNum).foreach(i => saved(i).inst := data(sel)(i))
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(0 until instFetchNum).foreach(i => saved(i).valid := inst_valid(i))
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}
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}
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}
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@ -221,13 +245,12 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}.elsewhen(io.axi.r.fire) {
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// * burst transport * //
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when(!io.axi.r.bits.last) {
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axi_cnt.inc()
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data_wstrb(lru(vset))(0) := data_wstrb(lru(vset))(instperbank - 1)
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(1 until instperbank).foreach(i => data_wstrb(lru(vset))(i) := data_wstrb(lru(vset))(i - 1))
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// 左移写掩码，写入下一个bank
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data_wstrb(lru(vindex)) := ((data_wstrb(lru(vindex)).asUInt << 1)(nbank - 1, 0)).asBools
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}.otherwise {
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rready := false.B
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data_wstrb(lru(vset)) := 0.U.asTypeOf(Vec(instperbank, UInt(4.W)))
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tag_wstrb(lru(vset)) := false.B
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rready := false.B
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data_wstrb(lru(vindex)).map(_ := false.B)
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tag_wstrb(lru(vindex)) := false.B
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}
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}.elsewhen(!io.axi.r.ready) {
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state := s_idle
|
||||
|
|
@ -236,8 +259,19 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
|
|||
is(s_save) {
|
||||
when(io.cpu.cpu_ready && !io.cpu.icache_stall) {
|
||||
state := s_idle
|
||||
(0 until instperbank).foreach(i => saved(i).valid := false.B)
|
||||
(0 until instFetchNum).foreach(i => saved(i).valid := false.B)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
println("ICache: ")
|
||||
println("nindex: " + nindex)
|
||||
println("nbank: " + nbank)
|
||||
println("bankOffsetWidth: " + bankOffsetWidth)
|
||||
println("bytesPerBank: " + bytesPerBank)
|
||||
println("tagWidth: " + tagWidth)
|
||||
println("indexWidth: " + indexWidth)
|
||||
println("offsetWidth: " + offsetWidth)
|
||||
println("size: " + rsize)
|
||||
println("len: " + rlen)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ class WriteOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) exten
|
|||
|
||||
class WriteOnlyMaskPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
|
||||
val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
|
||||
val en = Input(UInt(cacheConfig.bankWidth.W))
|
||||
val en = Input(UInt(cacheConfig.bytesPerBank.W))
|
||||
val data = Input(gen)
|
||||
}
|
||||
|
||||
|
|
@ -31,7 +31,7 @@ class ReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) exten
|
|||
|
||||
class MaskedReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
|
||||
val addr = Input(UInt(log2Ceil(cacheConfig.nindex * cacheConfig.nbank).W))
|
||||
val writeMask = Input(UInt(cacheConfig.bankWidth.W))
|
||||
val writeMask = Input(UInt(cacheConfig.bytesPerBank.W))
|
||||
val wdata = Input(gen)
|
||||
val rdata = Output(gen)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,13 +16,18 @@ import cpu.CpuConfig
|
|||
* @param cpuCfg
|
||||
* the implicit configuration for simulation and elaboration
|
||||
*/
|
||||
class SimpleDualPortRam(depth: Int, width: Int, byteAddressable: Boolean)(implicit
|
||||
val config: CpuConfig,
|
||||
) extends Module {
|
||||
class SimpleDualPortRam(
|
||||
depth: Int,
|
||||
width: Int,
|
||||
byteAddressable: Boolean
|
||||
)(
|
||||
implicit
|
||||
val config: CpuConfig)
|
||||
extends Module {
|
||||
require(isPow2(depth))
|
||||
require(
|
||||
width % 8 == 0 || !byteAddressable,
|
||||
"if memory is byte addressable, then the adderss width must be a multiple of 8",
|
||||
"if memory is byte addressable, then the adderss width must be a multiple of 8"
|
||||
)
|
||||
val waddridth = log2Ceil(depth)
|
||||
|
||||
|
|
@ -40,11 +45,11 @@ class SimpleDualPortRam(depth: Int, width: Int, byteAddressable: Boolean)(implic
|
|||
if (config.build) {
|
||||
val memory = Module(
|
||||
new SimpleDualPortRamIP(
|
||||
wdataidth = width,
|
||||
wdataidth = width,
|
||||
byteWriteWidth = if (byteAddressable) 8 else width,
|
||||
numberOfLines = depth,
|
||||
waddridth = waddridth,
|
||||
),
|
||||
numberOfLines = depth,
|
||||
waddridth = waddridth
|
||||
)
|
||||
)
|
||||
memory.io.clka := clock
|
||||
memory.io.clkb := clock
|
||||
|
|
@ -62,12 +67,12 @@ class SimpleDualPortRam(depth: Int, width: Int, byteAddressable: Boolean)(implic
|
|||
} else {
|
||||
assert(
|
||||
io.wstrb.orR || !io.wen,
|
||||
"when write port enable is high, write vector cannot be all 0",
|
||||
"when write port enable is high, write vector cannot be all 0"
|
||||
)
|
||||
if (byteAddressable) {
|
||||
val bank = SyncReadMem(depth, Vec(width / 8, UInt(8.W)))
|
||||
when(io.ren) {
|
||||
io.rdata := bank(io.raddr).asTypeOf(io.rdata)
|
||||
io.rdata := bank.read(io.raddr).asTypeOf(UInt(width.W))
|
||||
}.otherwise {
|
||||
io.rdata := DontCare
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ trait Constants extends CoreParameter {
|
|||
val EXC_WID = 16
|
||||
|
||||
// inst rom
|
||||
val INST_WID = XLEN
|
||||
val INST_WID = 32
|
||||
val INST_ADDR_WID = XLEN
|
||||
|
||||
// data ram
|
||||
|
|
|
|||
Loading…
Reference in New Issue