From 4355bc3b5d45a070378b336b40bc3a06bd8701a7 Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 26 Dec 2023 14:56:25 +0800 Subject: [PATCH] =?UTF-8?q?fix(fu):=20=E6=8F=90=E5=89=8D=E8=AE=BF=E5=AD=98?= =?UTF-8?q?=E5=9C=B0=E5=9D=80=E7=94=9F=E6=88=90=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/Fu.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index 2943407..fd98f4d 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -81,9 +81,9 @@ class Fu(implicit val config: CpuConfig) extends Module { val mem_addr = Seq.tabulate(config.commitNum)(i => Mux( - LSUOpType.isLoad(io.inst(i).info.op), - io.inst(i).src_info.src1_data + io.inst(i).info.imm, - io.inst(i).src_info.src1_data + LSUOpType.isAMO(io.inst(i).info.op), + io.inst(i).src_info.src1_data, + io.inst(i).src_info.src1_data + io.inst(i).info.imm ) ) io.dataMemory.addr := Mux(io.inst(0).info.fusel === FuType.lsu, mem_addr(0), mem_addr(1))