diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala
index e21a044..af2b7cd 100644
--- a/chisel/playground/src/defines/Const.scala
+++ b/chisel/playground/src/defines/Const.scala
@@ -39,9 +39,5 @@ object Instructions extends HasInstrType with CoreParameter {
   def NOP           = 0x00000013.U
   val DecodeDefault = List(InstrN, FuType.alu, ALUOpType.add)
   def DecodeTable = RVIInstr.table ++
-    (if (cpuConfig.hasMExtension) RVMInstr.table else Array.empty) ++
-    (if (cpuConfig.hasAExtension) RVAInstr.table else Array.empty) ++
-    (if (cpuConfig.hasUMode) Privileged.table else Array.empty) ++
-    (if (cpuConfig.hasZicsrExtension) RVZicsrInstr.table else Array.empty) ++
-    (if (cpuConfig.hasZifenceiExtension) RVZifenceiInstr.table else Array.empty)
+    (if (cpuConfig.hasMExtension) RVMInstr.table else Array.empty)
 }
diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala
index 975172e..d5783be 100644
--- a/chisel/playground/src/defines/isa/Instructions.scala
+++ b/chisel/playground/src/defines/isa/Instructions.scala
@@ -24,18 +24,16 @@ object SrcType {
 }
 
 object FuType {
-  def num     = 6
-  def alu     = "b000".U // arithmetic logic unit
-  def lsu     = "b001".U // load store unit
-  def mdu     = "b010".U // multiplication division unit
-  def csr     = "b011".U // control status register
-  def mou     = "b100".U // memory order unit
-  def bru     = "b101".U // branch unit
+  def num     = 4
+  def alu     = "b00".U // arithmetic logic unit
+  def mdu     = "b01".U // multiplication division unit
+  def lsu     = "b10".U // load store unit
+  def bru     = "b11".U // branch unit
   def apply() = UInt(log2Up(num).W)
 }
 
 object FuOpType {
-  def apply() = UInt(7.W)
+  def apply() = UInt(6.W)
 }
 
 // ALU
@@ -80,44 +78,20 @@ object BRUOpType {
 
 // load store unit
 object LSUOpType { //TODO: refactor LSU fuop
-  def lb  = "b0000000".U
-  def lh  = "b0000001".U
-  def lw  = "b0000010".U
-  def ld  = "b0000011".U
-  def lbu = "b0000100".U
-  def lhu = "b0000101".U
-  def lwu = "b0000110".U
-  def sb  = "b0001000".U
-  def sh  = "b0001001".U
-  def sw  = "b0001010".U
-  def sd  = "b0001011".U
+  def lb  = "b0000".U
+  def lh  = "b0001".U
+  def lw  = "b0010".U
+  def ld  = "b0011".U
+  def lbu = "b0100".U
+  def lhu = "b0101".U
+  def lwu = "b0110".U
+  def sb  = "b1000".U
+  def sh  = "b1001".U
+  def sw  = "b1010".U
+  def sd  = "b1011".U
 
-  def lr      = "b0100000".U
-  def sc      = "b0100001".U
-  def amoswap = "b0100010".U
-  def amoadd  = "b1100011".U
-  def amoxor  = "b0100100".U
-  def amoand  = "b0100101".U
-  def amoor   = "b0100110".U
-  def amomin  = "b0110111".U
-  def amomax  = "b0110000".U
-  def amominu = "b0110001".U
-  def amomaxu = "b0110010".U
-
-  def isAdd(func:   UInt) = func(6)
-  def isAtom(func:  UInt): Bool = func(5)
   def isStore(func: UInt): Bool = func(3)
-  def isLoad(func:  UInt): Bool = !isStore(func) & !isAtom(func)
-  def isLR(func:    UInt): Bool = func === lr
-  def isSC(func:    UInt): Bool = func === sc
-  def isAMO(func:   UInt): Bool = isAtom(func) && !isLR(func) && !isSC(func)
-}
-
-// memory order unit
-object MOUOpType {
-  def fence      = "b00".U
-  def fencei     = "b01".U
-  def sfence_vma = "b10".U
+  def isLoad(func:  UInt): Bool = !isStore(func)
 }
 
 // mul div unit
@@ -142,19 +116,3 @@ object MDUOpType {
   def isWordOp(op:  UInt) = op(3)
 }
 
-// csr unit
-object CSROpType {
-  def csrrw  = "b0001".U
-  def csrrs  = "b0010".U
-  def csrrc  = "b0011".U
-  def csrrwi = "b0101".U
-  def csrrsi = "b0110".U
-  def csrrci = "b0111".U
-
-  def ecall  = "b1000".U
-  def ebreak = "b1001".U
-  def mret   = "b1010".U
-  def sret   = "b1011".U
-
-  def isCSROp(op: UInt) = !op(3)
-}
diff --git a/chisel/playground/src/defines/isa/Privileged.scala b/chisel/playground/src/defines/isa/Privileged.scala
deleted file mode 100644
index 5bdc6bc..0000000
--- a/chisel/playground/src/defines/isa/Privileged.scala
+++ /dev/null
@@ -1,27 +0,0 @@
-package cpu.defines
-
-import chisel3._
-import chisel3.util._
-
-object Privileged extends HasInstrType with CoreParameter {
-  def ECALL      = BitPat("b000000000000_00000_000_00000_1110011")
-  def EBREAK     = BitPat("b000000000001_00000_000_00000_1110011")
-  def MRET       = BitPat("b001100000010_00000_000_00000_1110011")
-  def SRET       = BitPat("b000100000010_00000_000_00000_1110011")
-  def SFANCE_VMA = BitPat("b0001001_?????_?????_000_00000_1110011")
-  def FENCE      = BitPat("b????????????_?????_000_?????_0001111")
-  def WFI        = BitPat("b0001000_00101_00000_000_00000_1110011")
-
-  val table_s = Array(
-    SRET       -> List(InstrI, FuType.csr, CSROpType.sret),
-    SFANCE_VMA -> List(InstrR, FuType.mou, MOUOpType.sfence_vma)
-  )
-
-  val table = Array(
-    ECALL  -> List(InstrI, FuType.csr, CSROpType.ecall),
-    EBREAK -> List(InstrI, FuType.csr, CSROpType.ebreak),
-    MRET   -> List(InstrI, FuType.csr, CSROpType.mret),
-    FENCE  -> List(InstrS, FuType.mou, MOUOpType.fence), // nop    InstrS -> !wen
-    WFI    -> List(InstrI, FuType.alu, ALUOpType.add) // nop    rd = x0
-  ) ++ (if (cpuConfig.hasSMode) table_s else Array.empty)
-}
diff --git a/chisel/playground/src/defines/isa/RVA.scala b/chisel/playground/src/defines/isa/RVA.scala
deleted file mode 100644
index 5a2e01a..0000000
--- a/chisel/playground/src/defines/isa/RVA.scala
+++ /dev/null
@@ -1,42 +0,0 @@
-package cpu.defines
-
-import chisel3._
-import chisel3.util._
-
-object RVAInstr extends HasInstrType {
-  // Note: use instr(14,12) to distinguish D/W inst
-  // def LR      = BitPat("b00010??00000_?????_???_?????_0101111")
-  // def SC      = BitPat("b00011??00000_?????_???_?????_0101111")
-  def LR_D    = BitPat("b00010_??_00000_?????_011_?????_0101111")
-  def SC_D    = BitPat("b00011_??_?????_?????_011_?????_0101111")
-  def LR_W    = BitPat("b00010_??_00000_?????_010_?????_0101111")
-  def SC_W    = BitPat("b00011_??_?????_?????_010_?????_0101111")
-  def AMOSWAP = BitPat("b00001_??_?????_?????_01?_?????_0101111")
-  def AMOADD  = BitPat("b00000_??_?????_?????_01?_?????_0101111")
-  def AMOXOR  = BitPat("b00100_??_?????_?????_01?_?????_0101111")
-  def AMOAND  = BitPat("b01100_??_?????_?????_01?_?????_0101111")
-  def AMOOR   = BitPat("b01000_??_?????_?????_01?_?????_0101111")
-  def AMOMIN  = BitPat("b10000_??_?????_?????_01?_?????_0101111")
-  def AMOMAX  = BitPat("b10100_??_?????_?????_01?_?????_0101111")
-  def AMOMINU = BitPat("b11000_??_?????_?????_01?_?????_0101111")
-  def AMOMAXU = BitPat("b11100_??_?????_?????_01?_?????_0101111")
-  // funct3 === 010 or 011
-
-  val table = Array(
-    // LR          -> List(InstrI, FuType.lsu, LSUOpType.lr),
-    LR_D -> List(InstrI, FuType.lsu, LSUOpType.lr),
-    LR_W -> List(InstrI, FuType.lsu, LSUOpType.lr),
-    // SC          -> List(InstrS, FuType.lsu, LSUOpType.sc),
-    SC_D    -> List(InstrSA, FuType.lsu, LSUOpType.sc),
-    SC_W    -> List(InstrSA, FuType.lsu, LSUOpType.sc),
-    AMOSWAP -> List(InstrR, FuType.lsu, LSUOpType.amoswap),
-    AMOADD  -> List(InstrR, FuType.lsu, LSUOpType.amoadd),
-    AMOXOR  -> List(InstrR, FuType.lsu, LSUOpType.amoxor),
-    AMOAND  -> List(InstrR, FuType.lsu, LSUOpType.amoand),
-    AMOOR   -> List(InstrR, FuType.lsu, LSUOpType.amoor),
-    AMOMIN  -> List(InstrR, FuType.lsu, LSUOpType.amomin),
-    AMOMAX  -> List(InstrR, FuType.lsu, LSUOpType.amomax),
-    AMOMINU -> List(InstrR, FuType.lsu, LSUOpType.amominu),
-    AMOMAXU -> List(InstrR, FuType.lsu, LSUOpType.amomaxu)
-  )
-}
diff --git a/chisel/playground/src/defines/isa/RVZicsr.scala b/chisel/playground/src/defines/isa/RVZicsr.scala
deleted file mode 100644
index caea595..0000000
--- a/chisel/playground/src/defines/isa/RVZicsr.scala
+++ /dev/null
@@ -1,22 +0,0 @@
-package cpu.defines
-
-import chisel3._
-import chisel3.util._
-
-object RVZicsrInstr extends HasInstrType {
-  def CSRRW  = BitPat("b????????????_?????_001_?????_1110011")
-  def CSRRS  = BitPat("b????????????_?????_010_?????_1110011")
-  def CSRRC  = BitPat("b????????????_?????_011_?????_1110011")
-  def CSRRWI = BitPat("b????????????_?????_101_?????_1110011")
-  def CSRRSI = BitPat("b????????????_?????_110_?????_1110011")
-  def CSRRCI = BitPat("b????????????_?????_111_?????_1110011")
-
-  val table = Array(
-    CSRRW  -> List(InstrI, FuType.csr, CSROpType.csrrw),
-    CSRRS  -> List(InstrI, FuType.csr, CSROpType.csrrs),
-    CSRRC  -> List(InstrI, FuType.csr, CSROpType.csrrc),
-    CSRRWI -> List(InstrI, FuType.csr, CSROpType.csrrwi),
-    CSRRSI -> List(InstrI, FuType.csr, CSROpType.csrrsi),
-    CSRRCI -> List(InstrI, FuType.csr, CSROpType.csrrci)
-  )
-}
diff --git a/chisel/playground/src/defines/isa/RVZifencei.scala b/chisel/playground/src/defines/isa/RVZifencei.scala
deleted file mode 100644
index 29ff493..0000000
--- a/chisel/playground/src/defines/isa/RVZifencei.scala
+++ /dev/null
@@ -1,12 +0,0 @@
-package cpu.defines
-
-import chisel3._
-import chisel3.util._
-
-object RVZifenceiInstr extends HasInstrType {
-  def FENCEI = BitPat("b000000000000_00000_001_00000_0001111")
-
-  val table = Array(
-    FENCEI -> List(InstrB, FuType.mou, MOUOpType.fencei)
-  )
-}
diff --git a/difftest b/difftest
index e5cf2ff..e2b04f5 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit e5cf2ffe5854c0ba3cd50fd5e09dc67955d13e9c
+Subproject commit e2b04f50f1fa43f0153bac2a21f1bbcc98f050be