增加ptw的大致框架
This commit is contained in:
Liphen
parent
07490e0f13
commit
3a3680fb02
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@ -7,6 +7,7 @@ import cpu.CacheConfig
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import cpu.defines._
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import cpu.CpuConfig
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import cpu.defines.Const._
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import icache.mmu.AccessType
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/*
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整个宽度为PADDR_WID的地址
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@ -50,7 +51,7 @@ class WriteBufferUnit extends Bundle {
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val size = UInt(AXI_SIZE_WID.W)
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}
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class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Module {
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class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Module with Sv39Const with HasCSRConst {
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val nway = cacheConfig.nway
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val nindex = cacheConfig.nindex
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val nbank = cacheConfig.nbank
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@ -73,10 +74,16 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
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val axi = new DCache_AXIInterface()
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})
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// * fsm * //
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// dcache的状态机
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val s_idle :: s_uncached :: s_fence :: s_replace :: s_wait :: s_tlb_refill :: Nil = Enum(6)
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val state = RegInit(s_idle)
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// ptw的状态机
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val s_handshake :: s_send :: s_receive :: s_check :: s_set :: Nil = Enum(5)
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val ptw_state = RegInit(s_handshake)
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io.cpu.tlb.ptw.vpn.ready := false.B
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// ==========================================================
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// | tag | index | offset |
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// | | | bank index | bank offset |
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@ -191,6 +198,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
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io.cpu.rdata := Mux(state === s_wait, saved_rdata, data(bank_index)(select_way))
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io.cpu.tlb.addr := io.cpu.addr
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io.cpu.tlb.access_type := Mux(io.cpu.en && io.cpu.wen.orR, AccessType.store, AccessType.load)
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val bank_raddr = Mux(state === s_fence, dirty_index, Mux(use_next_addr, exe_index, replace_index))
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val tag_raddr = Mux(state === s_fence, dirty_index, tag_rindex)
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@ -334,7 +342,9 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
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}
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}
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}
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}.elsewhen(io.cpu.fence_i) {
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}.otherwise {
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io.cpu.tlb.ptw.vpn.ready := ptw_state === s_handshake
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when(io.cpu.fence_i) {
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// fence.i 需要将所有脏位为true的行写回
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when(dirty.asUInt.orR) {
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when(!writeFifo_busy) {
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@ -347,11 +357,13 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
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}
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}
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}
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}
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is(s_uncached) {
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when(arvalid && io.axi.ar.ready) {
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arvalid := false.B
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}
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when(io.axi.r.valid) {
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when(io.axi.r.fire) {
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rready := false.B
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saved_rdata := io.axi.r.bits.data
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acc_err := io.axi.r.bits.resp =/= RESP_OKEY.U
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state := s_wait
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@ -483,7 +495,170 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
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}
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}
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is(s_tlb_refill) {
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// TODO
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io.cpu.tlb.ptw.vpn.ready := ptw_state === s_handshake
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}
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}
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// ==========================================================
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// 实现页表访问，回填tlb
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val satp = io.cpu.tlb.csr.satp.asTypeOf(satpBundle)
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val mstatus = io.cpu.tlb.csr.mstatus.asTypeOf(new Mstatus)
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val mode = io.cpu.tlb.csr.mode
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val sum = mstatus.sum
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val mxr = mstatus.mxr
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val vpn = io.cpu.tlb.ptw.vpn.bits.asTypeOf(vpnBundle)
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val access_type = io.cpu.tlb.access_type
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val ppn = RegInit(0.U(ppnLen.W))
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val vpn_index = RegInit(0.U(log2Up(level).W)) // 页表访问的层级
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val pte = RegInit(0.U.asTypeOf(pteBundle)) // 页表项
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io.cpu.tlb.ptw.pte.valid := false.B
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io.cpu.tlb.ptw.pte.bits := DontCare
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io.cpu.tlb.ptw.pte.bits.access_fault := false.B
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io.cpu.tlb.ptw.pte.bits.page_fault := false.B
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require(AXI_DATA_WID == XLEN) // 目前只考虑了AXI_DATA_WID == XLEN的情况
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def raisePageFault(): Unit = {
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io.cpu.tlb.ptw.pte.valid := true.B
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io.cpu.tlb.ptw.pte.bits.page_fault := true.B
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ptw_state := s_handshake
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}
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def modeCheck(): Unit = {
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switch(mode) {
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is(ModeS) {
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when(pte.flag.u && !sum) {
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raisePageFault()
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}.otherwise {
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ptw_state := s_set
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}
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}
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is(ModeU) {
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when(!pte.flag.u) {
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raisePageFault()
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}.otherwise {
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ptw_state := s_set
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}
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}
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}
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}
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switch(ptw_state) {
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is(s_handshake) {
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// 页表访问虚地址握手
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when(io.cpu.tlb.ptw.vpn.valid) {
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vpn_index := (level - 1).U
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ppn := satp.ppn
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ptw_state := s_send
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}
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}
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is(s_send) {
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arvalid := true.B
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val vpnn = Mux1H(
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Seq(
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(vpn_index === 0.U) -> vpn.vpn0,
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(vpn_index === 1.U) -> vpn.vpn1,
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(vpn_index === 2.U) -> vpn.vpn2
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)
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)
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ar.addr := paddrApply(ppn, vpnn)
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ar.size := log2Ceil(AXI_DATA_WID / 8).U // 一个pte的大小是8字节
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ar.len := 0.U // 读一拍即可
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ptw_state := s_receive
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rready := true.B
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}
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is(s_receive) {
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when(io.axi.ar.fire) {
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arvalid := false.B
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}
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when(io.axi.r.fire) {
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rready := false.B
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val pte_temp = io.axi.r.bits.data.asTypeOf(pteBundle)
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when(!pte_temp.flag.v || !pte_temp.flag.r && pte_temp.flag.w) {
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raisePageFault()
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}.otherwise {
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when(pte_temp.flag.r || pte_temp.flag.x) {
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// 找到了叶子页
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pte := pte_temp
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ptw_state := s_check
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}.otherwise {
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// 该pte指向下一个页表
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vpn_index := vpn_index - 1.U
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when(vpn_index - 1.U < 0.U) {
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raisePageFault()
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}.otherwise {
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ppn := pte_temp.ppn
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ptw_state := s_send
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}
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}
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}
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}
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}
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is(s_check) {
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// 检查权限
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switch(access_type) {
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is(AccessType.load) {
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when(mxr) {
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when(!pte.flag.r && !pte.flag.x) {
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raisePageFault()
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}.otherwise {
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modeCheck()
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}
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}.otherwise {
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when(!pte.flag.r) {
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raisePageFault()
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}.otherwise {
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modeCheck()
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}
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}
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}
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is(AccessType.store) {
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when(!pte.flag.w) {
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raisePageFault()
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}.otherwise {
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modeCheck()
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}
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}
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is(AccessType.fetch) {
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when(!pte.flag.x) {
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raisePageFault()
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}.otherwise {
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modeCheck()
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}
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}
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}
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}
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is(s_set) {
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when(
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vpn_index > 0.U && (
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vpn_index === 1.U && pte.ppn(0) ||
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vpn_index === 2.U && pte.ppn(1, 0).orR
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)
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) {
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raisePageFault()
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}.elsewhen(!pte.flag.a || access_type === AccessType.store && !pte.flag.d) {
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raisePageFault() // 使用软件的方式设置脏位以及访问位
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}.otherwise {
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// 翻译成功
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io.cpu.tlb.ptw.pte.valid := true.B
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io.cpu.tlb.ptw.pte.bits.addr := ar.addr
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io.cpu.tlb.ptw.pte.bits.entry := pte
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val ppn_set = WireInit(ppnBundle)
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when(vpn_index === 2.U) {
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ppn_set.ppn2 := pte.ppn.asTypeOf(ppnBundle).ppn2
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ppn_set.ppn1 := vpn.vpn1
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ppn_set.ppn0 := vpn.vpn0
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}.elsewhen(vpn_index === 1.U) {
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ppn_set.ppn2 := pte.ppn.asTypeOf(ppnBundle).ppn2
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ppn_set.ppn1 := pte.ppn.asTypeOf(ppnBundle).ppn1
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ppn_set.ppn0 := vpn.vpn0
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}.otherwise {
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ppn_set := pte.ppn.asTypeOf(ppnBundle)
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}
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io.cpu.tlb.ptw.pte.bits.entry.ppn := ppn_set.asUInt
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ptw_state := s_handshake
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}
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}
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}
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@ -8,7 +8,25 @@ import cpu.CacheConfig
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import cpu.pipeline.execute.CsrTlb
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import cpu.CpuConfig
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class Tlb_Cache extends Bundle with Sv39Const {
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object AccessType {
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def apply() = UInt(2.W)
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def fetch = "b00".U
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def load = "b01".U
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def store = "b10".U
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}
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class Tlb_Ptw extends Bundle with Sv39Const {
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val vpn = Decoupled(UInt(vpnLen.W))
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val access_type = Output(AccessType())
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val pte = Flipped(Decoupled(new Bundle {
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val access_fault = Bool()
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val page_fault = Bool()
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val entry = pteBundle
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val addr = UInt(PADDR_WID.W)
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}))
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}
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class Tlb_ICache extends Bundle with Sv39Const {
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val addr = Input(UInt(XLEN.W))
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val complete_single_request = Input(Bool())
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@ -20,22 +38,17 @@ class Tlb_Cache extends Bundle with Sv39Const {
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val page_fault = Output(Bool())
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}
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class Tlb_Ptw extends Bundle with Sv39Const {
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val vpn = Decoupled(UInt(vpnLen.W))
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val pte = Flipped(Decoupled(new Bundle {
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val access_fault = Bool()
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val page_fault = Bool()
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val entry = pteBundle
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val addr = UInt(PADDR_WID.W)
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}))
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class Tlb_DCache extends Tlb_ICache {
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val ptw = new Tlb_Ptw()
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val access_type = Input(AccessType())
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val csr = new CsrTlb()
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}
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class Tlb extends Module with HasTlbConst with HasCSRConst {
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val io = IO(new Bundle {
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val icache = new Tlb_Cache()
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val dcache = new Tlb_Cache()
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val icache = new Tlb_ICache()
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val dcache = new Tlb_DCache()
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val csr = Flipped(new CsrTlb())
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val ptw = new Tlb_Ptw()
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val fence_vma = Input(new Bundle {
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val src1 = UInt(XLEN.W)
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val src2 = UInt(XLEN.W)
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@ -93,23 +106,13 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
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// 使用随机的方法替换TLB条目
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val replace_index = new Counter(cpuConfig.tlbEntries)
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replace_index.inc()
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val ipage_fault = RegInit(false.B)
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val dpage_fault = RegInit(false.B)
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val iaccess_fault = RegInit(false.B)
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val daccess_fault = RegInit(false.B)
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io.icache.hit := false.B
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io.dcache.hit := false.B
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io.icache.access_fault := iaccess_fault
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io.dcache.access_fault := daccess_fault
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io.icache.page_fault := ipage_fault
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io.dcache.page_fault := dpage_fault
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io.ptw.vpn.valid := false.B
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io.ptw.vpn.bits := DontCare
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io.ptw.pte.ready := true.B
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// ptw的请求标志，0位为指令tlb请求，1位为数据tlb请求
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val req_ptw = WireInit(VecInit(Seq.fill(2)(false.B)))
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@ -118,8 +121,8 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
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// 我们默认优先发送数据tlb的请求
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val ar_sel = Mux(ar_sel_lock, ar_sel_val, !req_ptw(0) && req_ptw(1))
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when(io.ptw.vpn.valid) {
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when(io.ptw.vpn.ready) {
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when(io.dcache.ptw.vpn.valid) {
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when(io.dcache.ptw.vpn.ready) {
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ar_sel_lock := false.B
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}.otherwise {
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ar_sel_lock := true.B
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@ -127,6 +130,20 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
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}
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}
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io.icache.hit := false.B
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io.dcache.hit := false.B
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io.icache.access_fault := iaccess_fault
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io.dcache.access_fault := daccess_fault
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io.icache.page_fault := ipage_fault
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io.dcache.page_fault := dpage_fault
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// 将ptw模块集成到dcache中，ptw通过dcache的axi进行内存访问
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io.dcache.ptw.vpn.valid := false.B
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io.dcache.ptw.access_type := Mux(ar_sel === 0.U, AccessType.fetch, io.dcache.access_type)
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io.dcache.ptw.vpn.bits := Mux(ar_sel === 0.U, ivpn, dvpn)
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io.dcache.ptw.pte.ready := true.B // 恒为true
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io.dcache.csr <> io.csr
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// 指令虚实地址转换
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switch(immu_state) {
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is(search_l1) {
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@ -167,24 +184,22 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
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is(search_l2) {
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when(il2_hit_vec.asUInt.orR) {
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immu_state := search_l1
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itlb := tlbl2(il2_hit_vec.indexWhere(_ === true.B))
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itlb := tlbl2(PriorityEncoder(il2_hit_vec))
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}.otherwise {
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req_ptw(0) := true.B
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when(ar_sel === 0.U) {
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io.ptw.vpn.valid := true.B
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io.ptw.vpn.bits := ivpn
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when(ar_sel === 0.U && io.dcache.ptw.vpn.ready) {
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io.dcache.ptw.vpn.valid := true.B
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immu_state := search_pte
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}
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}
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}
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is(search_pte) {
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io.ptw.vpn.valid := true.B
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io.ptw.vpn.bits := ivpn
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when(io.ptw.pte.valid) {
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when(io.ptw.pte.bits.access_fault) {
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io.icache.access_fault := true.B
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io.dcache.ptw.vpn.valid := true.B
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when(io.dcache.ptw.pte.valid) {
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when(io.dcache.ptw.pte.bits.access_fault) {
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iaccess_fault := true.B
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immu_state := search_fault
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}.elsewhen(io.ptw.pte.bits.page_fault) {
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}.elsewhen(io.dcache.ptw.pte.bits.page_fault) {
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ipage_fault := true.B
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immu_state := search_fault
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}.otherwise {
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@ -192,9 +207,9 @@ class Tlb extends Module with HasTlbConst with HasCSRConst {
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val replace_entry = Wire(tlbBundle)
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replace_entry.vpn := ivpn
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replace_entry.asid := satp.asid
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replace_entry.flag := io.ptw.pte.bits.entry.flag
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replace_entry.ppn := io.ptw.pte.bits.entry.ppn
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replace_entry.pteaddr := io.ptw.pte.bits.addr
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replace_entry.flag := io.dcache.ptw.pte.bits.entry.flag
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replace_entry.ppn := io.dcache.ptw.pte.bits.entry.ppn
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replace_entry.pteaddr := io.dcache.ptw.pte.bits.addr
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tlbl2(replace_index.value) := replace_entry
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itlb := replace_entry
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immu_state := search_l1
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@ -5,7 +5,7 @@ import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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import icache.mmu.Tlb_Cache
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import icache.mmu.{Tlb_DCache, Tlb_ICache}
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class ExceptionInfo extends Bundle {
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val exception = Vec(EXC_WID, Bool())
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@ -121,7 +121,7 @@ class Cache_ICache(implicit val cpuConfig: CpuConfig) extends Bundle {
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val icache_stall = Input(Bool()) // icache_stall
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// tlb
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val tlb = new Tlb_Cache()
|
||||
val tlb = new Tlb_ICache()
|
||||
}
|
||||
|
||||
// cpu to dcache
|
||||
|
|
@ -140,7 +140,7 @@ class Cache_DCache extends Bundle {
|
|||
val acc_err = Input(Bool())
|
||||
val dcache_ready = Input(Bool())
|
||||
|
||||
val tlb = new Tlb_Cache()
|
||||
val tlb = new Tlb_DCache()
|
||||
}
|
||||
|
||||
// axi
|
||||
|
|
|
|||
|
|
@ -66,6 +66,12 @@ trait Sv39Const extends CoreParameter {
|
|||
val offset = UInt(pageOffsetLen.W)
|
||||
}
|
||||
|
||||
def ppnBundle = new Bundle {
|
||||
val ppn2 = UInt(ppn2Len.W)
|
||||
val ppn1 = UInt(ppn1Len.W)
|
||||
val ppn0 = UInt(ppn0Len.W)
|
||||
}
|
||||
|
||||
def paddrApply(ppn: UInt, vpnn: UInt): UInt = {
|
||||
Cat(Cat(ppn, vpnn), 0.U(3.W))
|
||||
}
|
||||
|
|
@ -75,14 +81,14 @@ trait Sv39Const extends CoreParameter {
|
|||
val ppn = UInt(ppnLen.W)
|
||||
val rsw = UInt(2.W)
|
||||
val flag = new Bundle {
|
||||
val d = UInt(1.W)
|
||||
val a = UInt(1.W)
|
||||
val g = UInt(1.W)
|
||||
val u = UInt(1.W)
|
||||
val x = UInt(1.W)
|
||||
val w = UInt(1.W)
|
||||
val r = UInt(1.W)
|
||||
val v = UInt(1.W)
|
||||
val d = Bool()
|
||||
val a = Bool()
|
||||
val g = Bool()
|
||||
val u = Bool()
|
||||
val x = Bool()
|
||||
val w = Bool()
|
||||
val r = Bool()
|
||||
val v = Bool()
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue