fix(csr): 修复exe的valid
This commit is contained in:
Liphen
parent
8f9fe9362f
commit
39d5e8e043
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@ -242,13 +242,13 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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mipWire.t.m := mtip
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mipWire.e.m := meip
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mipWire.s.m := msip
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val seip = meip
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val mip_has_interrupt = WireInit(mip.asTypeOf(new Interrupt()))
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mip_has_interrupt.e.s := mip.asTypeOf(new Interrupt).e.s | seip
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val seip = meip
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val mip_raise_interrupt = WireInit(mip.asTypeOf(new Interrupt()))
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mip_raise_interrupt.e.s := mip.asTypeOf(new Interrupt).e.s | seip
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val mstatusBundle = mstatus.asTypeOf(new Mstatus())
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val ideleg = (mideleg & mip_has_interrupt.asUInt)
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val ideleg = (mideleg & mip_raise_interrupt.asUInt)
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def priviledgedEnableDetect(x: Bool): Bool = Mux(
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x,
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((mode === ModeS) && mstatusBundle.ie.s) || (mode < ModeS),
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@ -257,7 +257,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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val interrupt_enable = Wire(Vec(INT_WID, Bool()))
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interrupt_enable.zip(ideleg.asBools).map { case (x, y) => x := priviledgedEnableDetect(y) }
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io.decodeUnit.interrupt := mie(INT_WID - 1, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
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io.decodeUnit.interrupt := mie(INT_WID - 1, 0) & mip_raise_interrupt.asUInt & interrupt_enable.asUInt
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// 优先使用inst0的信息
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val mem_pc = io.memoryUnit.in.pc
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@ -267,11 +267,11 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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val mem_valid = mem_inst_info.valid
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val mem_addr = mem_inst(31, 20)
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val has_exception = mem_ex.exception.asUInt.orR
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val has_interrupt = mem_ex.interrupt.asUInt.orR
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val has_exc_int = has_exception || has_interrupt
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val raise_exception = mem_ex.exception.asUInt.orR
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val raise_interrupt = mem_ex.interrupt.asUInt.orR
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val raise_exc_int = raise_exception || raise_interrupt
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// 不带前缀的信号为exe阶段的信号
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val valid = io.executeUnit.in.valid && !has_exc_int
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val valid = io.executeUnit.in.valid && !io.memoryUnit.out.flush // mem发生flush时，轻刷掉exe的信号
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val info = io.executeUnit.in.info
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val op = io.executeUnit.in.info.op
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val fusel = io.executeUnit.in.info.fusel
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@ -317,33 +317,33 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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val exceptionNO = ExcPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.exception(i), i.U, sum))
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val interruptNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum))
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val causeNO = (has_interrupt << (XLEN - 1)) | Mux(has_interrupt, interruptNO, exceptionNO)
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val causeNO = (raise_interrupt << (XLEN - 1)) | Mux(raise_interrupt, interruptNO, exceptionNO)
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val has_instrPageFault = mem_ex.exception(instrPageFault)
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val has_loadPageFault = mem_ex.exception(loadPageFault)
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val has_storePageFault = mem_ex.exception(storePageFault)
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val has_loadAddrMisaligned = mem_ex.exception(loadAddrMisaligned)
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val has_storeAddrMisaligned = mem_ex.exception(storeAddrMisaligned)
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val has_instrAddrMisaligned = mem_ex.exception(instrAddrMisaligned)
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val raise_instrPageFault = mem_ex.exception(instrPageFault)
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val raise_loadPageFault = mem_ex.exception(loadPageFault)
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val raise_storePageFault = mem_ex.exception(storePageFault)
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val raise_loadAddrMisaligned = mem_ex.exception(loadAddrMisaligned)
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val raise_storeAddrMisaligned = mem_ex.exception(storeAddrMisaligned)
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val raise_instrAddrMisaligned = mem_ex.exception(instrAddrMisaligned)
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val deleg = Mux(has_interrupt, mideleg, medeleg)
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val deleg = Mux(raise_interrupt, mideleg, medeleg)
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val delegS = (deleg(causeNO(log2Ceil(EXC_WID) - 1, 0))) && (mode < ModeM)
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val tval_wen = has_interrupt ||
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!(has_instrPageFault ||
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has_loadPageFault ||
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has_storePageFault ||
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has_instrAddrMisaligned ||
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has_loadAddrMisaligned ||
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has_storeAddrMisaligned)
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val tval_wen = raise_interrupt ||
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!(raise_instrPageFault ||
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raise_loadPageFault ||
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raise_storePageFault ||
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raise_instrAddrMisaligned ||
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raise_loadAddrMisaligned ||
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raise_storeAddrMisaligned)
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when(
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has_instrPageFault ||
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has_loadPageFault ||
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has_storePageFault ||
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has_instrAddrMisaligned ||
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has_loadAddrMisaligned ||
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has_storeAddrMisaligned
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raise_instrPageFault ||
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raise_loadPageFault ||
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raise_storePageFault ||
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raise_instrAddrMisaligned ||
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raise_loadAddrMisaligned ||
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raise_storeAddrMisaligned
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) {
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val tval = SignedExtend(mem_ex.tval, XLEN)
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when(mode === ModeM) {
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@ -353,7 +353,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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}
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}
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when(has_exc_int) {
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when(raise_exc_int) {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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@ -383,7 +383,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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val trap_target = Wire(UInt(VADDR_WID.W))
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val tvec = Mux(delegS, stvec, mtvec)
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trap_target := (tvec(VADDR_WID - 1, 2) << 2) + Mux(
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tvec(0) && has_interrupt,
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tvec(0) && raise_interrupt,
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(causeNO << 2),
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0.U
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)
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@ -425,6 +425,6 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
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io.executeUnit.out.rdata := rdata
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io.executeUnit.out.flush := write_satp
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io.executeUnit.out.target := io.executeUnit.in.pc + 4.U
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io.memoryUnit.out.flush := has_exc_int || ret
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io.memoryUnit.out.target := Mux(has_exc_int, trap_target, ret_target)
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io.memoryUnit.out.flush := raise_exc_int || ret
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io.memoryUnit.out.target := Mux(raise_exc_int, trap_target, ret_target)
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}
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