diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index b596f99..3f18046 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -18,7 +18,7 @@ class SrcInfo extends Bundle {
 }
 
 class RdInfo extends Bundle {
-  val wdata = UInt(XLEN.W)
+  val wdata = Vec(FuType.num, UInt(XLEN.W))
 }
 
 class InstInfo extends Bundle {
diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala
index fb3df7c..4c1060c 100644
--- a/chisel/playground/src/pipeline/decoder/Decoder.scala
+++ b/chisel/playground/src/pipeline/decoder/Decoder.scala
@@ -43,14 +43,14 @@ class Decoder extends Module with HasInstrType {
   io.out.inst_info.reg2_raddr := Mux(src2Type === SrcType.reg, rt, 0.U)
   io.out.inst_info.fusel      := fuType
   io.out.inst_info.op         := fuOpType
-  when(fuType === FuType.bru) {
-    def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
-    when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.inst_info.op := ALUOpType.call }
-    when(fuOpType === ALUOpType.jalr) {
-      when(isLink(rs)) { io.out.inst_info.op := ALUOpType.ret }
-      when(isLink(rd)) { io.out.inst_info.op := ALUOpType.call }
-    }
-  }
+  // when(fuType === FuType.bru) {
+  //   def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
+  //   when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.inst_info.op := ALUOpType.call }
+  //   when(fuOpType === ALUOpType.jalr) {
+  //     when(isLink(rs)) { io.out.inst_info.op := ALUOpType.ret }
+  //     when(isLink(rd)) { io.out.inst_info.op := ALUOpType.call }
+  //   }
+  // }
   io.out.inst_info.reg_wen   := isrfWen(instrType)
   io.out.inst_info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
   io.out.inst_info.imm := LookupTree(
diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala
index 9d785c6..2b35438 100644
--- a/chisel/playground/src/pipeline/execute/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/Csr.scala
@@ -33,6 +33,7 @@ class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
   val out = Output(new Bundle {
     val rdata    = Vec(config.fuNum, UInt(DATA_WID.W))
     val trap_ill = Bool()
+    val ex       = Vec(config.fuNum, new ExceptionInfo())
   })
 }
 
@@ -226,12 +227,10 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata)
 
   // CSR inst decode
-  val ret      = Wire(Bool())
-  val isEbreak = addr === privEbreak && op === CSROpType.jmp
-  val isEcall  = addr === privEcall && op === CSROpType.jmp
-  val isMret   = addr === privMret && op === CSROpType.jmp
-  val isSret   = addr === privSret && op === CSROpType.jmp
-  val isUret   = addr === privUret && op === CSROpType.jmp
+  val ret    = Wire(Bool())
+  val isMret = addr === privMret && op === CSROpType.jmp
+  val isSret = addr === privSret && op === CSROpType.jmp
+  val isUret = addr === privUret && op === CSROpType.jmp
   ret := isMret || isSret || isUret
 
   val csrExceptionVec = Wire(Vec(16, Bool()))
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index 5ddf218..58961c1 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -107,22 +107,32 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.memoryStage.inst0.mem.sel       := accessMemCtrl.inst.map(_.mem_sel)
   io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
 
-  io.memoryStage.inst0.pc            := io.executeStage.inst0.pc
-  io.memoryStage.inst0.inst_info     := io.executeStage.inst0.inst_info
-  io.memoryStage.inst0.rd_info.wdata := fu.inst(0).result
-  io.memoryStage.inst0.ex := Mux(
-    io.executeStage.inst0.inst_info.fusel === FuType.lsu,
-    accessMemCtrl.inst(0).ex.out,
-    fu.inst(0).ex.out
+  io.memoryStage.inst0.pc                        := io.executeStage.inst0.pc
+  io.memoryStage.inst0.inst_info                 := io.executeStage.inst0.inst_info
+  io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
+  io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
+  io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
+  io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
+  io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
+  io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
+    Seq(
+      FuType.lsu -> accessMemCtrl.inst(0).ex.out,
+      FuType.csr -> io.csr.out.ex(0)
+    )
   )
 
-  io.memoryStage.inst1.pc            := io.executeStage.inst1.pc
-  io.memoryStage.inst1.inst_info     := io.executeStage.inst1.inst_info
-  io.memoryStage.inst1.rd_info.wdata := fu.inst(1).result
-  io.memoryStage.inst1.ex := Mux(
-    io.executeStage.inst1.inst_info.fusel === FuType.lsu,
-    accessMemCtrl.inst(1).ex.out,
-    fu.inst(1).ex.out
+  io.memoryStage.inst1.pc                        := io.executeStage.inst1.pc
+  io.memoryStage.inst1.inst_info                 := io.executeStage.inst1.inst_info
+  io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
+  io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
+  io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
+  io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
+  io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
+  io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(
+    Seq(
+      FuType.lsu -> accessMemCtrl.inst(1).ex.out,
+      FuType.csr -> io.csr.out.ex(1)
+    )
   )
 
   io.decoderUnit.forward(0).exe.wen      := io.memoryStage.inst0.inst_info.reg_wen
diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index bce97d5..a71c75d 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -22,7 +22,10 @@ class Fu(implicit val config: CpuConfig) extends Module {
           val in  = Input(new ExceptionInfo())
           val out = Output(new ExceptionInfo())
         }
-        val result = Output(UInt(DATA_WID.W))
+        val result = Output(new Bundle {
+          val mdu = UInt(DATA_WID.W)
+          val alu = UInt(DATA_WID.W)
+        })
       }
     )
     val csr_rdata = Input(Vec(config.fuNum, UInt(DATA_WID.W)))
@@ -52,9 +55,9 @@ class Fu(implicit val config: CpuConfig) extends Module {
     // alu(i).io.mul.ready         := mul.ready
     // alu(i).io.div.ready         := div.ready
     // alu(i).io.div.result        := div.result
-    alu(i).io.csr_rdata         := io.csr_rdata(i)
-    io.inst(i).ex.out           := io.inst(i).ex.in
-    io.inst(i).ex.out.excode    := io.inst(i).ex.in.excode
+    alu(i).io.csr_rdata      := io.csr_rdata(i)
+    io.inst(i).ex.out        := io.inst(i).ex.in
+    io.inst(i).ex.out.excode := io.inst(i).ex.in.excode
   }
 
 //   mul.src1        := Mux(io.inst(0).mul_en, io.inst(0).src_info.src1_data, io.inst(1).src_info.src1_data)
@@ -73,10 +76,12 @@ class Fu(implicit val config: CpuConfig) extends Module {
 //     (io.inst.map(_.mul_en).reduce(_ || _) && !mul.ready)
   io.stall_req := false.B
 
-  io.inst(0).result := Mux(
+  io.inst(0).result.alu := Mux(
     ALUOpType.isBru(io.inst(0).inst_info.op),
     io.inst(0).pc + 4.U,
     alu(0).io.result
   )
-  io.inst(1).result := alu(1).io.result
+  io.inst(0).result.mdu := DontCare
+  io.inst(1).result.alu := alu(1).io.result
+  io.inst(1).result.mdu := DontCare
 }
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 8facc00..19495da 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -18,13 +18,13 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
   io.regfile(0).wen := io.writeBackStage.inst0.inst_info.reg_wen &&
     io.ctrl.allow_to_go && !io.writeBackStage.inst0.ex.excode.asUInt.orR
   io.regfile(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
-  io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata
+  io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
 
   io.regfile(1).wen :=
     io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go &&
       !io.writeBackStage.inst0.ex.excode.asUInt.orR && !io.writeBackStage.inst1.ex.excode.asUInt.orR
   io.regfile(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
-  io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata
+  io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
 
   if (config.hasCommitBuffer) {
     val buffer = Module(new CommitBuffer()).io