From 347def990aa0ca6a49f670f7067ca8a94ee6bb51 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 13 Nov 2023 15:56:31 +0800 Subject: [PATCH] =?UTF-8?q?test:=20=E5=A2=9E=E5=8A=A0=E9=83=A8=E4=BB=B6?= =?UTF-8?q?=E6=B5=8B=E8=AF=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/Makefile | 7 ++++--- chisel/playground/test/src/TestMain.scala | 15 +++++++++++++++ chisel/playground/test/src/test.scala | 18 ------------------ 3 files changed, 19 insertions(+), 21 deletions(-) create mode 100644 chisel/playground/test/src/TestMain.scala delete mode 100644 chisel/playground/test/src/test.scala diff --git a/chisel/Makefile b/chisel/Makefile index 6655f60..8089c93 100644 --- a/chisel/Makefile +++ b/chisel/Makefile @@ -2,14 +2,15 @@ BUILD_DIR = ./build export PATH := $(PATH):$(abspath ./utils) -test: - mill -i __.test - verilog: $(MAKE) clean mkdir -p $(BUILD_DIR) mill -i __.test.runMain Elaborate -td $(BUILD_DIR) +test: + @echo "make test" + mill -i __.test.runMain TestMain -td $(BUILD_DIR) + help: mill -i __.test.runMain Elaborate --help diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala new file mode 100644 index 0000000..f96906f --- /dev/null +++ b/chisel/playground/test/src/TestMain.scala @@ -0,0 +1,15 @@ +import cpu._ +import circt.stage._ +import cache.CacheAXIInterface + +object TestMain extends App { + implicit val config = new CpuConfig() + def top = new CacheAXIInterface() + val useMFC = false // use MLIR-based firrtl compiler + val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) + if (useMFC) { + (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) + } else { + (new chisel3.stage.ChiselStage).execute(args, generator) + } +} \ No newline at end of file diff --git a/chisel/playground/test/src/test.scala b/chisel/playground/test/src/test.scala deleted file mode 100644 index 7e3e19e..0000000 --- a/chisel/playground/test/src/test.scala +++ /dev/null @@ -1,18 +0,0 @@ -// package cpu - -// import chisel3.stage.ChiselGeneratorAnnotation - -// import cpu.CpuConfig -// import cpu.pipeline.execute._ -// import cpu.pipeline.memory.DataMemoryAccess -// import cpu.pipeline.memory.MemoryUnit -// import cpu.pipeline.writeback.WriteBackUnit -// import cpu.pipeline.fetch.PreDecoder - -// object testMain extends App { -// implicit val config = new CpuConfig() -// (new chisel3.stage.ChiselStage).execute( -// Array("--target-dir", "generated"), -// Seq(ChiselGeneratorAnnotation(() => new PreDecoder())), -// ) -// }