From 333ced6e193d271661d86d831f4aeb56f8348cda Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 6 May 2024 16:05:40 +0800 Subject: [PATCH] =?UTF-8?q?fix(if):=20=E4=BF=AE=E5=A4=8D=E7=AC=AC=E4=B8=80?= =?UTF-8?q?=E4=B8=AApc=E5=88=9D=E5=A7=8B=E5=80=BC=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/build.sc | 2 +- chisel/playground/src/pipeline/fetch/FetchUnit.scala | 5 +---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/chisel/build.sc b/chisel/build.sc index 3cf92e2..55432d4 100644 --- a/chisel/build.sc +++ b/chisel/build.sc @@ -30,7 +30,7 @@ object playground extends ScalaModule with ScalafmtModule { m => override def ivyDeps = m.ivyDeps() ++ Agg( ivy"com.lihaoyi::utest:0.8.1", if (useChisel5) ivy"edu.berkeley.cs::chiseltest:5.0.0" else - if (useChisel5) ivy"edu.berkeley.cs::chiseltest:6.1.0" else + if (useChisel6) ivy"edu.berkeley.cs::chiseltest:6.1.0" else ivy"edu.berkeley.cs::chiseltest:0.6.0", ) } diff --git a/chisel/playground/src/pipeline/fetch/FetchUnit.scala b/chisel/playground/src/pipeline/fetch/FetchUnit.scala index aa526f5..916dc34 100644 --- a/chisel/playground/src/pipeline/fetch/FetchUnit.scala +++ b/chisel/playground/src/pipeline/fetch/FetchUnit.scala @@ -12,11 +12,8 @@ class FetchUnit extends Module { val decodeStage = new FetchUnitDecodeUnit() val instSram = new InstSram() }) - val pc = RegNext(io.instSram.addr, PC_INIT) - val pc_next_temp = Wire(UInt(XLEN.W)) - - pc_next_temp := pc + val pc = RegNext(io.instSram.addr, (PC_INIT - 4.U)) io.instSram.addr := MuxCase( pc + 4.U,