diff --git a/chisel/build.sc b/chisel/build.sc
index 3cf92e2..55432d4 100644
--- a/chisel/build.sc
+++ b/chisel/build.sc
@@ -30,7 +30,7 @@ object playground extends ScalaModule with ScalafmtModule { m =>
     override def ivyDeps = m.ivyDeps() ++ Agg(
       ivy"com.lihaoyi::utest:0.8.1",
       if (useChisel5) ivy"edu.berkeley.cs::chiseltest:5.0.0" else
-      if (useChisel5) ivy"edu.berkeley.cs::chiseltest:6.1.0" else
+      if (useChisel6) ivy"edu.berkeley.cs::chiseltest:6.1.0" else
       ivy"edu.berkeley.cs::chiseltest:0.6.0",
     )
   }
diff --git a/chisel/playground/src/pipeline/fetch/FetchUnit.scala b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
index aa526f5..916dc34 100644
--- a/chisel/playground/src/pipeline/fetch/FetchUnit.scala
+++ b/chisel/playground/src/pipeline/fetch/FetchUnit.scala
@@ -12,11 +12,8 @@ class FetchUnit extends Module {
     val decodeStage = new FetchUnitDecodeUnit()
     val instSram    = new InstSram()
   })
-  val pc = RegNext(io.instSram.addr, PC_INIT)
 
-  val pc_next_temp = Wire(UInt(XLEN.W))
-
-  pc_next_temp := pc
+  val pc = RegNext(io.instSram.addr, (PC_INIT - 4.U))
 
   io.instSram.addr := MuxCase(
     pc + 4.U,