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tval增加非法指令来源

This commit is contained in:
Liphen 2024-01-20 17:30:18 +08:00
parent 5e338f97a6
commit 3277f13a3f
5 changed files with 43 additions and 55 deletions
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2
chisel/playground/src/defines/Bundles.scala
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@ -11,7 +11,7 @@ import cpu.pipeline.memory.Mou
class ExceptionInfo extends Bundle { class ExceptionInfo extends Bundle {
val exception = Vec(EXC_WID, Bool()) val exception = Vec(EXC_WID, Bool())
val interrupt = Vec(INT_WID, Bool()) val interrupt = Vec(INT_WID, Bool())
val tval = UInt(XLEN.W) val tval = Vec(EXC_WID, UInt(XLEN.W))
} }
class ExtInterrupt extends Bundle { class ExtInterrupt extends Bundle {

36
chisel/playground/src/pipeline/decode/DecodeUnit.scala
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@ -134,16 +134,14 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
info(0).op === CSROpType.jmp && mode === ModeS && info(0).fusel === FuType.csr info(0).op === CSROpType.jmp && mode === ModeS && info(0).fusel === FuType.csr
io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall && io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
info(0).op === CSROpType.jmp && mode === ModeU && info(0).fusel === FuType.csr info(0).op === CSROpType.jmp && mode === ModeU && info(0).fusel === FuType.csr
// tval注意先后顺序 io.executeStage.inst0.ex.tval.map(_ := DontCare)
io.executeStage.inst0.ex.tval := MuxCase( io.executeStage.inst0.ex.tval(instrPageFault) := pc(0)
0.U, io.executeStage.inst0.ex.tval(instrAccessFault) := pc(0)
Seq( io.executeStage.inst0.ex.tval(illegalInstr) := info(0).inst
io.executeStage.inst0.ex.exception(instrPageFault) -> pc(0), io.executeStage.inst0.ex.tval(instrAddrMisaligned) := Mux(
io.executeStage.inst0.ex.exception(instrAccessFault) -> pc(0), io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
!info(0).inst_legal -> info(0).inst, io.fetchUnit.target,
pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(0), pc(0)
(io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
)
) )
io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
@ -181,16 +179,14 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
info(1).op === CSROpType.jmp && mode === ModeS && info(1).fusel === FuType.csr info(1).op === CSROpType.jmp && mode === ModeS && info(1).fusel === FuType.csr
io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall && io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
info(1).op === CSROpType.jmp && mode === ModeU && info(1).fusel === FuType.csr info(1).op === CSROpType.jmp && mode === ModeU && info(1).fusel === FuType.csr
io.executeStage.inst1.ex.tval.map(_ := DontCare)
io.executeStage.inst1.ex.tval := MuxCase( io.executeStage.inst1.ex.tval(instrPageFault) := pc(1)
0.U, io.executeStage.inst1.ex.tval(instrAccessFault) := pc(1)
Seq( io.executeStage.inst1.ex.tval(illegalInstr) := info(1).inst
io.executeStage.inst1.ex.exception(instrPageFault) -> pc(1), io.executeStage.inst1.ex.tval(instrAddrMisaligned) := Mux(
io.executeStage.inst1.ex.exception(instrAccessFault) -> pc(1), io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
!info(1).inst_legal -> info(1).inst, io.fetchUnit.target,
pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR -> pc(1), pc(1)
(io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch) -> io.fetchUnit.target
)
) )
} }

16
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
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@ -149,9 +149,11 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
) )
io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) || io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
when(io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR) { io.memoryStage.inst0.ex.tval(instrAddrMisaligned) := Mux(
io.memoryStage.inst0.ex.tval := io.fetchUnit.target io.executeStage.inst0.ex.exception(instrAddrMisaligned),
} io.executeStage.inst0.ex.tval(instrAddrMisaligned),
io.fetchUnit.target
)
io.memoryStage.inst1.pc := io.executeStage.inst1.pc io.memoryStage.inst1.pc := io.executeStage.inst1.pc
io.memoryStage.inst1.info := io.executeStage.inst1.info io.memoryStage.inst1.info := io.executeStage.inst1.info
@ -173,9 +175,11 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
) )
io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) || io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
when(io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR) { io.memoryStage.inst1.ex.tval(instrAddrMisaligned) := Mux(
io.memoryStage.inst1.ex.tval := io.fetchUnit.target io.executeStage.inst1.ex.exception(instrAddrMisaligned),
} io.executeStage.inst1.ex.tval(instrAddrMisaligned),
io.fetchUnit.target
)
io.decodeUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen io.decodeUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
io.decodeUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr io.decodeUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr

36
chisel/playground/src/pipeline/execute/fu/Csr.scala
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@ -319,33 +319,14 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
val interruptNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum)) val interruptNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum))
val causeNO = (raise_interrupt << (XLEN - 1)) | Mux(raise_interrupt, interruptNO, exceptionNO) val causeNO = (raise_interrupt << (XLEN - 1)) | Mux(raise_interrupt, interruptNO, exceptionNO)
val raise_instrPageFault = mem_ex.exception(instrPageFault)
val raise_loadPageFault = mem_ex.exception(loadPageFault)
val raise_storePageFault = mem_ex.exception(storePageFault)
val raise_loadAddrMisaligned = mem_ex.exception(loadAddrMisaligned)
val raise_storeAddrMisaligned = mem_ex.exception(storeAddrMisaligned)
val raise_instrAddrMisaligned = mem_ex.exception(instrAddrMisaligned)
val deleg = Mux(raise_interrupt, mideleg, medeleg) val deleg = Mux(raise_interrupt, mideleg, medeleg)
val delegS = (deleg(causeNO(log2Ceil(EXC_WID) - 1, 0))) && (mode < ModeM) val delegS = (deleg(causeNO(log2Ceil(EXC_WID) - 1, 0))) && (mode < ModeM)
val tval_wen = raise_interrupt || val tval_wen = raise_interrupt ||
!(raise_instrPageFault || !raise_exception
raise_loadPageFault ||
raise_storePageFault ||
raise_instrAddrMisaligned ||
raise_loadAddrMisaligned ||
raise_storeAddrMisaligned)
when( when(raise_exception) {
raise_instrPageFault || val tval = mem_ex.tval(exceptionNO)
raise_loadPageFault ||
raise_storePageFault ||
raise_instrAddrMisaligned ||
raise_loadAddrMisaligned ||
raise_storeAddrMisaligned
) {
val tval = SignedExtend(mem_ex.tval, XLEN)
when(mode === ModeM) { when(mode === ModeM) {
mtval := tval mtval := tval
}.otherwise { }.otherwise {
@ -422,9 +403,10 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
io.executeUnit.out.ex := io.executeUnit.in.ex io.executeUnit.out.ex := io.executeUnit.in.ex
io.executeUnit.out.ex.exception(illegalInstr) := io.executeUnit.out.ex.exception(illegalInstr) :=
(illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr) (illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr)
io.executeUnit.out.rdata := rdata io.executeUnit.out.ex.tval(illegalInstr) := io.executeUnit.in.info.inst
io.executeUnit.out.flush := write_satp io.executeUnit.out.rdata := rdata
io.executeUnit.out.target := io.executeUnit.in.pc + 4.U io.executeUnit.out.flush := write_satp
io.memoryUnit.out.flush := raise_exc_int || ret io.executeUnit.out.target := io.executeUnit.in.pc + 4.U
io.memoryUnit.out.target := Mux(raise_exc_int, trap_target, ret_target) io.memoryUnit.out.flush := raise_exc_int || ret
io.memoryUnit.out.target := Mux(raise_exc_int, trap_target, ret_target)
} }

8
chisel/playground/src/pipeline/memory/Lsu.scala
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@ -203,7 +203,13 @@ class Lsu(implicit val cpuConfig: CpuConfig) extends Module {
io.memoryUnit.out.ex.exception(storeAccessFault) := (storeReq || scReq || amoReq) && lsExe.out.addr_misaligned io.memoryUnit.out.ex.exception(storeAccessFault) := (storeReq || scReq || amoReq) && lsExe.out.addr_misaligned
io.memoryUnit.out.ex.exception(storePageFault) := (storeReq || scReq || amoReq) && lsExe.out.page_fault io.memoryUnit.out.ex.exception(storePageFault) := (storeReq || scReq || amoReq) && lsExe.out.page_fault
io.memoryUnit.out.ex.tval := io.dataMemory.out.addr io.memoryUnit.out.ex.tval(loadAddrMisaligned) := io.dataMemory.out.addr
io.memoryUnit.out.ex.tval(loadAccessFault) := io.dataMemory.out.addr
io.memoryUnit.out.ex.tval(loadPageFault) := io.dataMemory.out.addr
io.memoryUnit.out.ex.tval(storeAddrMisaligned) := io.dataMemory.out.addr
io.memoryUnit.out.ex.tval(storeAccessFault) := io.dataMemory.out.addr
io.memoryUnit.out.ex.tval(storePageFault) := io.dataMemory.out.addr
io.memoryUnit.out.rdata := MuxCase( io.memoryUnit.out.rdata := MuxCase(
lsExe.out.rdata, lsExe.out.rdata,
Seq( Seq(