From 31eadb3bf378e5f534def96b8e54976a412e7c98 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Thu, 23 Nov 2023 21:51:57 +0800
Subject: [PATCH] =?UTF-8?q?feat:=20=E6=88=90=E5=8A=9F=E8=AF=BB=E5=8F=96?=
 =?UTF-8?q?=E5=88=B0=E6=8C=87=E4=BB=A4?=
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---
 chisel/Makefile                               |  8 ++--
 chisel/playground/src/Core.scala              |  2 +-
 chisel/playground/src/cache/ICache.scala      | 41 ++++++++++---------
 .../src/pipeline/execute/ExecuteUnit.scala    |  2 +-
 4 files changed, 28 insertions(+), 25 deletions(-)

diff --git a/chisel/Makefile b/chisel/Makefile
index d5e0796..5b0ccfd 100644
--- a/chisel/Makefile
+++ b/chisel/Makefile
@@ -9,10 +9,10 @@ verilog:
 	mkdir -p $(BUILD_DIR)
 	mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
 
-func:
-	$(MAKE) verilog
-	cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
-	cd $(DIFF_WORK_DIR) && make func
+# func:
+# 	$(MAKE) verilog
+# 	cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
+# 	cd $(DIFF_WORK_DIR) && make func
 
 test:
 	@echo "make test"
diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index f38169a..9113408 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -142,7 +142,7 @@ class Core(implicit val config: CpuConfig) extends Module {
     executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei
   io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
     memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
-  io.inst.en    := !instFifo.full
+  io.inst.en    := !instFifo.full && !reset.asBool
   io.inst.ready := !ctrl.fetchUnit.allow_to_go
   io.data.ready := !ctrl.memoryUnit.allow_to_go
 }
diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index ea567c2..da88fb2 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -18,18 +18,21 @@ class ICache(implicit config: CpuConfig) extends Module {
   val status                                  = RegInit(s_idle)
 
   io.cpu.valid.map(_ := status === s_finishwait)
-  io.cpu.addr_err := io.cpu.addr(0)(1, 0).orR
-  val addr_err = io.cpu.addr(0).orR
+  io.cpu.addr_err    := io.cpu.addr(0)(1, 0).orR
+  val addr_err = io.cpu.addr(0)(63, 32).orR
 
   // default
-  io.axi.ar.id    := 0.U
-  io.axi.ar.addr  := 0.U
-  io.axi.ar.len   := 0.U
-  io.axi.ar.size  := 2.U
-  io.axi.ar.lock  := 0.U
-  io.axi.ar.burst := BURST_FIXED.U
-  val arvalid = RegInit(false.B)
-  io.axi.ar.valid    := arvalid
+  val ar = RegInit(0.U.asTypeOf(new Bundle {
+    val valid = Bool()
+    val addr  = UInt(32.W)
+  }))
+  io.axi.ar.id       := 0.U
+  io.axi.ar.addr     := ar.addr
+  io.axi.ar.len      := 0.U
+  io.axi.ar.size     := 2.U
+  io.axi.ar.lock     := 0.U
+  io.axi.ar.burst    := BURST_FIXED.U
+  io.axi.ar.valid    := ar.valid
   io.axi.ar.prot     := 0.U
   io.axi.ar.cache    := 0.U
   io.axi.r.ready     := true.B
@@ -44,19 +47,19 @@ class ICache(implicit config: CpuConfig) extends Module {
           io.cpu.acc_err := true.B
           status         := s_finishwait
         }.otherwise {
-          io.axi.ar.addr := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
-          arvalid        := true.B
-          status         := s_read
+          ar.addr  := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
+          ar.valid := true.B
+          status   := s_read
         }
       }
     }
     is(s_read) {
       when(io.axi.ar.ready) {
-        arvalid := false.B
+        ar.valid := false.B
       }
       when(io.axi.r.valid) {
-        io.cpu.rdata(0) := Mux(io.axi.ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
-        io.cpu.rdata(1) := Mux(io.axi.ar.addr(2), 0.U, io.axi.r.data(63, 32))
+        io.cpu.rdata(0) := Mux(ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
+        io.cpu.rdata(1) := Mux(ar.addr(2), 0.U, io.axi.r.data(63, 32))
         io.cpu.acc_err  := io.axi.r.resp =/= RESP_OKEY.U
         status          := s_finishwait
       }
@@ -69,9 +72,9 @@ class ICache(implicit config: CpuConfig) extends Module {
             io.cpu.acc_err := true.B
             status         := s_finishwait
           }.otherwise {
-            io.axi.ar.addr := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
-            arvalid        := true.B
-            status         := s_read
+            ar.addr  := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
+            ar.valid := true.B
+            status   := s_read
           }
         }
       }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index d6a9145..04ed125 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -97,7 +97,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.bpu.branch_inst      := io.executeStage.inst0.jb_info.branch_inst
 
   io.fetchUnit.branch := io.ctrl.allow_to_go &&
-    (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
+    (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) && io.executeStage.inst0.valid
   io.fetchUnit.target := MuxCase(
     io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
     Seq(