diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index 9113408..3a6b62a 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -143,6 +143,6 @@ class Core(implicit val config: CpuConfig) extends Module {
   io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
     memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
   io.inst.en    := !instFifo.full && !reset.asBool
-  io.inst.ready := !ctrl.fetchUnit.allow_to_go
-  io.data.ready := !ctrl.memoryUnit.allow_to_go
+  io.inst.ready := ctrl.fetchUnit.allow_to_go
+  io.data.ready := ctrl.memoryUnit.allow_to_go
 }
diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index da88fb2..b80e489 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -18,36 +18,41 @@ class ICache(implicit config: CpuConfig) extends Module {
   val status                                  = RegInit(s_idle)
 
   io.cpu.valid.map(_ := status === s_finishwait)
-  io.cpu.addr_err    := io.cpu.addr(0)(1, 0).orR
-  val addr_err = io.cpu.addr(0)(63, 32).orR
+  val read_next_addr = (status === s_idle || status === s_finishwait)
+  io.cpu.addr_err := io.cpu.addr(read_next_addr)(1, 0).orR
+  val addr_err = io.cpu.addr(read_next_addr)(63, 32).orR
+  val raddr    = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))
 
   // default
   val ar = RegInit(0.U.asTypeOf(new Bundle {
     val valid = Bool()
     val addr  = UInt(32.W)
   }))
+  val rdata   = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U(32.W))))
+  val acc_err = RegInit(false.B)
   io.axi.ar.id       := 0.U
   io.axi.ar.addr     := ar.addr
-  io.axi.ar.len      := 0.U
+  io.axi.ar.len      := (config.instFetchNum - 1).U
   io.axi.ar.size     := 2.U
   io.axi.ar.lock     := 0.U
-  io.axi.ar.burst    := BURST_FIXED.U
+  io.axi.ar.burst    := BURST_INCR.U
   io.axi.ar.valid    := ar.valid
   io.axi.ar.prot     := 0.U
   io.axi.ar.cache    := 0.U
   io.axi.r.ready     := true.B
   io.cpu.rdata.map(_ := 0.U)
-  io.cpu.acc_err     := false.B
+  io.cpu.acc_err     := acc_err
   io.cpu.stall       := false.B
+  io.cpu.rdata       := rdata
 
   switch(status) {
     is(s_idle) {
       when(io.cpu.en) {
         when(addr_err) {
-          io.cpu.acc_err := true.B
-          status         := s_finishwait
+          acc_err := true.B
+          status  := s_finishwait
         }.otherwise {
-          ar.addr  := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
+          ar.addr  := raddr
           ar.valid := true.B
           status   := s_read
         }
@@ -58,21 +63,21 @@ class ICache(implicit config: CpuConfig) extends Module {
         ar.valid := false.B
       }
       when(io.axi.r.valid) {
-        io.cpu.rdata(0) := Mux(ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
-        io.cpu.rdata(1) := Mux(ar.addr(2), 0.U, io.axi.r.data(63, 32))
-        io.cpu.acc_err  := io.axi.r.resp =/= RESP_OKEY.U
-        status          := s_finishwait
+        rdata(0) := Mux(ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
+        rdata(1) := Mux(ar.addr(2), 0.U, io.axi.r.data(63, 32))
+        acc_err  := io.axi.r.resp =/= RESP_OKEY.U
+        status   := s_finishwait
       }
     }
     is(s_finishwait) {
       when(io.cpu.ready) {
-        io.cpu.acc_err := false.B
+        acc_err := false.B
         when(io.cpu.en) {
           when(addr_err) {
-            io.cpu.acc_err := true.B
-            status         := s_finishwait
+            acc_err := true.B
+            status  := s_finishwait
           }.otherwise {
-            ar.addr  := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
+            ar.addr  := raddr
             ar.valid := true.B
             status   := s_read
           }