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fix(ptw): 修改working逻辑

This commit is contained in:
Liphen 2024-01-17 15:53:24 +08:00
parent 0b91cc5bea
commit 2ee4b18581
1 changed files with 8 additions and 9 deletions
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17
chisel/playground/src/cache/DCache.scala vendored
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@ -83,10 +83,10 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
val ptw_state = RegInit(ptw_handshake) val ptw_state = RegInit(ptw_handshake)
// 临时寄存器 // 临时寄存器
val ptw_working = ptw_state =/= ptw_handshake
val ptw_scratch = RegInit(0.U.asTypeOf(new Bundle { val ptw_scratch = RegInit(0.U.asTypeOf(new Bundle {
val paddr = cacheAddr val paddr = cacheAddr
val replace = Bool() val replace = Bool()
val working = Bool()
})) }))
io.cpu.tlb.ptw.vpn.ready := false.B io.cpu.tlb.ptw.vpn.ready := false.B
@ -371,7 +371,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
} }
} }
}.otherwise { }.otherwise {
io.cpu.tlb.ptw.vpn.ready := ptw_state === ptw_handshake io.cpu.tlb.ptw.vpn.ready := !ptw_working
when(io.cpu.fence_i) { when(io.cpu.fence_i) {
// fence.i 需要将所有脏位为true的行写回 // fence.i 需要将所有脏位为true的行写回
when(dirty.asUInt.orR) { when(dirty.asUInt.orR) {
@ -488,7 +488,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
valid(replace_index)(replace_way) := true.B valid(replace_index)(replace_way) := true.B
do_replace := false.B do_replace := false.B
ptw_scratch.replace := false.B ptw_scratch.replace := false.B
when(ptw_scratch.working && io.cpu.tlb.ptw.access_type =/= AccessType.fetch) { when(ptw_working && io.cpu.tlb.ptw.access_type =/= AccessType.fetch) {
// ptw复用的模式 // ptw复用的模式
state := s_tlb_refill state := s_tlb_refill
}.otherwise { }.otherwise {
@ -505,7 +505,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
rready := true.B rready := true.B
burst.wstrb(replace_way) := 1.U // 先写入第一块bank burst.wstrb(replace_way) := 1.U // 先写入第一块bank
tag_wstrb(replace_way) := true.B tag_wstrb(replace_way) := true.B
when(!ptw_scratch.working) { when(!ptw_working) {
// dcache的普通模式 // dcache的普通模式
// for ar axi // for ar axi
ar.addr := Cat(io.cpu.tlb.paddr(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W)) ar.addr := Cat(io.cpu.tlb.paddr(PADDR_WID - 1, offsetWidth), 0.U(offsetWidth.W))
@ -536,7 +536,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
} }
} }
is(s_tlb_refill) { is(s_tlb_refill) {
io.cpu.tlb.ptw.vpn.ready := ptw_state === ptw_handshake io.cpu.tlb.ptw.vpn.ready := !ptw_working
when(io.cpu.tlb.access_fault) { when(io.cpu.tlb.access_fault) {
access_fault := true.B access_fault := true.B
state := s_wait state := s_wait
@ -600,10 +600,9 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
is(ptw_handshake) { is(ptw_handshake) {
// 页表访问虚地址握手 // 页表访问虚地址握手
when(io.cpu.tlb.ptw.vpn.valid) { when(io.cpu.tlb.ptw.vpn.valid) {
vpn_index := (level - 1).U vpn_index := (level - 1).U
ppn := satp.ppn ppn := satp.ppn
ptw_state := ptw_send ptw_state := ptw_send
ptw_scratch.working := true.B
} }
} }
is(ptw_send) { is(ptw_send) {