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重构mem stage级接口

This commit is contained in:
Liphen 2024-01-22 14:17:20 +08:00
parent 4448b9639b
commit 2c63e880ea
4 changed files with 73 additions and 102 deletions
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8
chisel/playground/src/pipeline/execute/ExecuteStage.scala
View File

@ -7,7 +7,7 @@ import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
import cpu.CpuConfig
class IdExeInstInfo extends Bundle {
class IdExeInfo extends Bundle {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
@ -23,7 +23,7 @@ class JumpBranchInfo extends Bundle {
}
class DecodeUnitExecuteUnit(implicit cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new IdExeInstInfo())
val inst = Vec(cpuConfig.commitNum, new IdExeInfo())
val jump_branch_info = new JumpBranchInfo()
}
@ -37,12 +37,12 @@ class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
val executeUnit = Output(new DecodeUnitExecuteUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeInstInfo())))
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeInfo())))
val jump_branch_info = RegInit(0.U.asTypeOf(new JumpBranchInfo()))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear(i)) {
inst(i) := 0.U.asTypeOf(new IdExeInstInfo())
inst(i) := 0.U.asTypeOf(new IdExeInfo())
}.elsewhen(io.ctrl.allow_to_go(i)) {
inst(i) := io.decodeUnit.inst(i)
}

76
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -127,66 +127,40 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
io.ctrl.fu_stall := fu.stall_req
io.memoryStage.inst0.pc := io.executeStage.inst(0).pc
io.memoryStage.inst0.info := io.executeStage.inst(0).info
io.memoryStage.inst0.src_info := io.executeStage.inst(0).src_info
io.memoryStage.inst0.rd_info.wdata := DontCare
io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
io.memoryStage.inst0.rd_info.wdata(FuType.bru) := io.executeStage.inst(0).pc + 4.U
io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
for (i <- 0 until (cpuConfig.commitNum)) {
io.memoryStage.inst(i).pc := io.executeStage.inst(i).pc
io.memoryStage.inst(i).info := io.executeStage.inst(i).info
io.memoryStage.inst(i).src_info := io.executeStage.inst(i).src_info
io.memoryStage.inst(i).rd_info.wdata := DontCare
io.memoryStage.inst(i).rd_info.wdata(FuType.alu) := fu.inst(i).result.alu
io.memoryStage.inst(i).rd_info.wdata(FuType.bru) := io.executeStage.inst(i).pc + 4.U
io.memoryStage.inst(i).rd_info.wdata(FuType.mdu) := fu.inst(i).result.mdu
io.memoryStage.inst(i).rd_info.wdata(FuType.csr) := io.csr.out.rdata
val has_ex0 =
(HasExcInt(io.executeStage.inst(0).ex)) && io.executeStage.inst(0).info.valid
io.memoryStage.inst0.ex := Mux(
(HasExcInt(io.executeStage.inst(i).ex)) && io.executeStage.inst(i).info.valid
io.memoryStage.inst(i).ex := Mux(
has_ex0,
io.executeStage.inst(0).ex,
MuxLookup(io.executeStage.inst(0).info.fusel, io.executeStage.inst(0).ex)(
io.executeStage.inst(i).ex,
MuxLookup(io.executeStage.inst(i).info.fusel, io.executeStage.inst(i).ex)(
Seq(
FuType.csr -> io.csr.out.ex
)
)
)
io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst(0).ex.exception(instrAddrMisaligned) ||
io.memoryStage
.inst(i)
.ex
.exception(instrAddrMisaligned) := io.executeStage.inst(i).ex.exception(instrAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
io.memoryStage.inst0.ex.tval(instrAddrMisaligned) := Mux(
io.executeStage.inst(0).ex.exception(instrAddrMisaligned),
io.executeStage.inst(0).ex.tval(instrAddrMisaligned),
io.memoryStage.inst(i).ex.tval(instrAddrMisaligned) := Mux(
io.executeStage.inst(i).ex.exception(instrAddrMisaligned),
io.executeStage.inst(i).ex.tval(instrAddrMisaligned),
io.fetchUnit.target
)
io.memoryStage.inst1.pc := io.executeStage.inst(1).pc
io.memoryStage.inst1.info := io.executeStage.inst(1).info
io.memoryStage.inst1.src_info := io.executeStage.inst(1).src_info
io.memoryStage.inst1.rd_info.wdata := DontCare
io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
val has_ex1 =
(HasExcInt(io.executeStage.inst(1).ex)) && io.executeStage.inst(1).info.valid
io.memoryStage.inst1.ex := Mux(
has_ex1,
io.executeStage.inst(1).ex,
MuxLookup(io.executeStage.inst(1).info.fusel, io.executeStage.inst(1).ex)(
Seq(
FuType.csr -> io.csr.out.ex
)
)
)
io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst(1).ex.exception(instrAddrMisaligned) ||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
io.memoryStage.inst1.ex.tval(instrAddrMisaligned) := Mux(
io.executeStage.inst(1).ex.exception(instrAddrMisaligned),
io.executeStage.inst(1).ex.tval(instrAddrMisaligned),
io.fetchUnit.target
)
io.decodeUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
io.decodeUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr
io.decodeUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel)
io.decodeUnit.forward(0).exe_mem_wreg := io.ctrl.inst(0).mem_wreg
io.decodeUnit.forward(1).exe.wen := io.memoryStage.inst1.info.reg_wen
io.decodeUnit.forward(1).exe.waddr := io.memoryStage.inst1.info.reg_waddr
io.decodeUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel)
io.decodeUnit.forward(1).exe_mem_wreg := io.ctrl.inst(1).mem_wreg
io.decodeUnit.forward(i).exe.wen := io.memoryStage.inst(i).info.reg_wen
io.decodeUnit.forward(i).exe.waddr := io.memoryStage.inst(i).info.reg_waddr
io.decodeUnit.forward(i).exe.wdata := io.memoryStage.inst(i).rd_info.wdata(io.memoryStage.inst(i).info.fusel)
io.decodeUnit.forward(i).exe_mem_wreg := io.ctrl.inst(i).mem_wreg
}
}

19
chisel/playground/src/pipeline/memory/MemoryStage.scala
View File

@ -6,7 +6,7 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class ExeMemInst extends Bundle {
class ExeMemInfo extends Bundle {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val rd_info = new RdInfo()
@ -15,8 +15,7 @@ class ExeMemInst extends Bundle {
}
class ExecuteUnitMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst0 = new ExeMemInst()
val inst1 = new ExeMemInst()
val inst = Vec(cpuConfig.commitNum, new ExeMemInfo())
}
class MemoryStage(implicit val cpuConfig: CpuConfig) extends Module {
@ -28,17 +27,15 @@ class MemoryStage(implicit val cpuConfig: CpuConfig) extends Module {
val executeUnit = Input(new ExecuteUnitMemoryUnit())
val memoryUnit = Output(new ExecuteUnitMemoryUnit())
})
val inst0 = RegInit(0.U.asTypeOf(new ExeMemInst()))
val inst1 = RegInit(0.U.asTypeOf(new ExeMemInst()))
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new ExeMemInfo())))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear) {
inst0 := 0.U.asTypeOf(new ExeMemInst())
inst1 := 0.U.asTypeOf(new ExeMemInst())
inst(i) := 0.U.asTypeOf(new ExeMemInfo())
}.elsewhen(io.ctrl.allow_to_go) {
inst0 := io.executeUnit.inst0
inst1 := io.executeUnit.inst1
inst(i) := io.executeUnit.inst(i)
}
}
io.memoryUnit.inst0 := inst0
io.memoryUnit.inst1 := inst1
io.memoryUnit.inst := inst
}

56
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -26,37 +26,37 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
val lsu = Module(new Lsu()).io
val mou = Module(new Mou()).io
mou.in.info := io.memoryStage.inst0.info
mou.in.pc := io.memoryStage.inst0.pc
mou.in.info := io.memoryStage.inst(0).info
mou.in.pc := io.memoryStage.inst(0).pc
val mem_sel = VecInit(
io.memoryStage.inst0.info.valid &&
io.memoryStage.inst0.info.fusel === FuType.lsu &&
!HasExcInt(io.memoryStage.inst0.ex),
io.memoryStage.inst1.info.valid &&
io.memoryStage.inst1.info.fusel === FuType.lsu &&
!HasExcInt(io.memoryStage.inst1.ex) && !HasExcInt(io.memoryStage.inst0.ex)
io.memoryStage.inst(0).info.valid &&
io.memoryStage.inst(0).info.fusel === FuType.lsu &&
!HasExcInt(io.memoryStage.inst(0).ex),
io.memoryStage.inst(1).info.valid &&
io.memoryStage.inst(1).info.fusel === FuType.lsu &&
!HasExcInt(io.memoryStage.inst(1).ex) && !HasExcInt(io.memoryStage.inst(0).ex)
)
lsu.memoryUnit.in.mem_en := mem_sel.reduce(_ || _)
lsu.memoryUnit.in.info := MuxCase(
0.U.asTypeOf(new InstInfo()),
Seq(
mem_sel(0) -> io.memoryStage.inst0.info,
mem_sel(1) -> io.memoryStage.inst1.info
mem_sel(0) -> io.memoryStage.inst(0).info,
mem_sel(1) -> io.memoryStage.inst(1).info
)
)
lsu.memoryUnit.in.src_info := MuxCase(
0.U.asTypeOf(new SrcInfo()),
Seq(
mem_sel(0) -> io.memoryStage.inst0.src_info,
mem_sel(1) -> io.memoryStage.inst1.src_info
mem_sel(0) -> io.memoryStage.inst(0).src_info,
mem_sel(1) -> io.memoryStage.inst(1).src_info
)
)
lsu.memoryUnit.in.ex := MuxCase(
0.U.asTypeOf(new ExceptionInfo()),
Seq(
mem_sel(0) -> io.memoryStage.inst0.ex,
mem_sel(1) -> io.memoryStage.inst1.ex
mem_sel(0) -> io.memoryStage.inst(0).ex,
mem_sel(1) -> io.memoryStage.inst(1).ex
)
)
lsu.dataMemory <> io.dataMemory
@ -68,8 +68,8 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
io.csr.in.pc := MuxCase(
0.U,
Seq(
(io.ctrl.allow_to_go && csr_sel) -> io.memoryStage.inst0.pc,
(io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst1.pc
(io.ctrl.allow_to_go && csr_sel) -> io.memoryStage.inst(0).pc,
(io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst(1).pc
)
)
io.csr.in.ex := MuxCase(
@ -82,8 +82,8 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
io.csr.in.info := MuxCase(
0.U.asTypeOf(new InstInfo()),
Seq(
(io.ctrl.allow_to_go && csr_sel) -> io.memoryStage.inst0.info,
(io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst1.info
(io.ctrl.allow_to_go && csr_sel) -> io.memoryStage.inst(0).info,
(io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst(1).info
)
)
@ -100,26 +100,26 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
io.decodeUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
io.decodeUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
io.writeBackStage.inst0.info := io.memoryStage.inst0.info
io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata
io.writeBackStage.inst0.pc := io.memoryStage.inst(0).pc
io.writeBackStage.inst0.info := io.memoryStage.inst(0).info
io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst(0).rd_info.wdata
io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
io.writeBackStage.inst0.ex := Mux(
mem_sel(0),
lsu.memoryUnit.out.ex,
io.memoryStage.inst0.ex
io.memoryStage.inst(0).ex
)
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
io.writeBackStage.inst1.info := io.memoryStage.inst1.info
io.writeBackStage.inst1.info.valid := io.memoryStage.inst1.info.valid &&
io.writeBackStage.inst1.pc := io.memoryStage.inst(1).pc
io.writeBackStage.inst1.info := io.memoryStage.inst(1).info
io.writeBackStage.inst1.info.valid := io.memoryStage.inst(1).info.valid &&
!(io.fetchUnit.flush && csr_sel) // 指令0导致flush时，不应该提交指令1
io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata
io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst(1).rd_info.wdata
io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
io.writeBackStage.inst1.ex := Mux(
mem_sel(1),
lsu.memoryUnit.out.ex,
io.memoryStage.inst1.ex
io.memoryStage.inst(1).ex
)
io.ctrl.flush := io.fetchUnit.flush
@ -129,7 +129,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
io.ctrl.complete_single_request := lsu.memoryUnit.out.complete_single_request
io.ctrl.sfence_vma.valid := mou.out.sfence_vma
io.ctrl.sfence_vma.src_info := io.memoryStage.inst0.src_info
io.ctrl.sfence_vma.src_info := io.memoryStage.inst(0).src_info
io.fetchUnit.flush := io.ctrl.allow_to_go && (io.csr.out.flush || mou.out.flush)
io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.target, mou.out.target)