修改sram信号定义

chisel/playground/src/defines/Bundles.scala

@@ -89,18 +89,18 @@ class WriteBackCtrl extends Bundle {
 
 class InstSram extends Bundle {
   val en    = Output(Bool())
-  val addr  = Output(UInt(AXI_ADDR_WID.W))
-  val wdata = Output(UInt(INST_WID.W))
-  val wen   = Output(UInt((INST_WID / 8).W))
-  val rdata = Input(UInt(INST_WID.W))
+  val addr  = Output(UInt(SRAM_ADDR_WID.W))
+  val wdata = Output(UInt(INST_SRAM_DATA_WID.W))
+  val wen   = Output(UInt(INST_SRAM_WEN_WID.W))
+  val rdata = Input(UInt(INST_SRAM_DATA_WID.W))
 }
 
 class DataSram extends Bundle {
   val en    = Output(Bool())
-  val addr  = Output(UInt(AXI_ADDR_WID.W))
-  val wdata = Output(UInt(XLEN.W))
-  val wen   = Output(UInt(AXI_STRB_WID.W))
-  val rdata = Input(UInt(XLEN.W))
+  val addr  = Output(UInt(SRAM_ADDR_WID.W))
+  val wdata = Output(UInt(DATA_SRAM_DATA_WID.W))
+  val wen   = Output(UInt(DATA_SRAM_WEN_WID.W))
+  val rdata = Input(UInt(DATA_SRAM_DATA_WID.W))
 }
 
 class DEBUG extends Bundle {

chisel/playground/src/defines/Const.scala

@@ -26,28 +26,14 @@ trait Constants extends CoreParameter {
   val REG_ADDR_WID = 5
 }
 
-trait AXIConst extends Constants {
-  // AXI
-  val BURST_FIXED    = 0
-  val BURST_INCR     = 1
-  val BURST_WRAP     = 2
-  val BURST_RESERVED = 3
-
-  val RESP_OKAY   = 0
-
-  val AXI_ID_WID    = 4
-  val AXI_ADDR_WID  = PADDR_WID // 32
-  val AXI_DATA_WID  = 64
-  val AXI_STRB_WID  = 8
-  val AXI_RESP_WID  = 2
-  val AXI_LEN_WID   = 8
-  val AXI_SIZE_WID  = 3
-  val AXI_BURST_WID = 2
-  val AXI_LOCK_WID  = 2
-  val AXI_CACHE_WID = 4
-  val AXI_PROT_WID  = 3
+trait SRAMConst extends Constants {
+  val SRAM_ADDR_WID      = PADDR_WID // 32
+  val DATA_SRAM_DATA_WID = XLEN
+  val DATA_SRAM_WEN_WID  = XLEN / 8
+  val INST_SRAM_DATA_WID = INST_WID
+  val INST_SRAM_WEN_WID  = INST_WID / 8
 }
-object Const extends Constants with AXIConst with HasExceptionNO
+object Const extends Constants with SRAMConst
 
 object Instructions extends HasInstrType with CoreParameter {
   def NOP           = 0x00000013.U