From 2a09884e0f2e444b254e0f15a09eb1710bc5f0fc Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 21 Jan 2024 13:51:46 +0800 Subject: [PATCH] =?UTF-8?q?fix(fu):=20=E4=BF=AE=E6=94=B9=E5=9C=B0=E5=9D=80?= =?UTF-8?q?=E5=89=8D=E9=80=92=E9=80=BB=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/Fu.scala | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index 91eb375..1089656 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -86,5 +86,11 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module { io.inst(i).src_info.src1_data + io.inst(i).info.imm ) ) - io.dataMemory.addr := Mux(io.inst(0).info.fusel === FuType.lsu, mem_addr(0), mem_addr(1)) + // 当mem级访存发生stall时，mem_addr_last不变 + val mem_addr_last = RegEnable(io.dataMemory.addr, io.ctrl.allow_to_go) + io.dataMemory.addr := Mux( + !io.ctrl.allow_to_go, + mem_addr_last, + Mux(io.inst(0).info.fusel === FuType.lsu, mem_addr(0), mem_addr(1)) + ) }